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GlobalFoundries tests 20nm chip

Posted: 01 Sep 2011 ?? ?Print Version ?Bookmark and Share

Keywords:20nm? chip design? double patterning?

With the help of design tools from other design companies, GlobalFoundries Inc. has manufactured a 20nm test chip. The chip was tested through double patterning and was implemented together with other EDA partners.

Cadence Design Systems Inc., Magma Design Automation Inc., Mentor Graphics Corp. and Synopsys Inc. each contributed in the testing and implementation of the said test chip. The test chip supported double patterning library preparation, placement, clock tree synthesis, hold fixing, routing and post-route optimization. The design flow supported extraction, static timing analysis and physical verification.

GlobalFoundries said it will make the test chip and its libraries including complete flow scripts available to customers who wish to evaluate 20nm technology.





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