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Use spread spectrum clock generators for EMI reduction in digital systems (Part 2)

Posted: 05 Sep 2011 ?? ?Print Version ?Bookmark and Share

Keywords:spread? spread spectrum clock generator? jitter?

The second part of this series tackles the types of spread. Based on the position of start and stop frequencies with respect to reference frequency, spread spectrum clock generator (SSCGs) can be classified in the following three categories.

Down Spread: Modulates the reference clock downwards and restricts the maximum frequency of the modulated signal to the frequency of reference clock. Useful in applications which are frequency sensitive and are already operating at the maximum rate they can operate.

Down spread (%) = (f / fo) 100,

where f = freffmin

A down spread provides the spread spectrum clock while maintaining the maximum allowed frequency in the system.

Center Spread: Modulates the output clock symmetrically about the reference frequency (i.e., the output frequency will increase and decrease the same amount above and below the center frequency). A 1% center spread will provide a total variation of 2% with 1% variation above and another 1% below the reference frequency.

Center spread (%) = ? (f / fo) 100,

where f = fmaxfmin

Center spread is useful in systems where the frequency restriction doesn't apply.

Up Spread: Up-spread is exactly opposite down-spread. The reference clock is modulated upwards by restricting the lower limit to reference clock.

Up spread (%) = (f / fo) 100,

where f = fmaxfref

Precautions when using spread spectrum clock
Jitter: One of the significant disadvantages of using a spread spectrum clock is that it cannot be used in systems where clock accuracy is of major concern; e.g. for Ethernet or CAN bus applications. Engineers must take special care in selecting spread clocks and the spread amount for their application requirements as it may introduce substantial jitter number to the clock signal. This jitter may adversely affect system performance, causing critical setup and hold time violations, higher bit error rates, and PLL unlock issues. Jitter can be of different types and can have different effects on the performance of a system.

a) Period jitter (PJ): PJ refers to the maximum change in a clock's output transition from its ideal position. PJ is generally measured as the peak-to-peak period variation evaluated over time, typically ten thousand cycles, which is simply the difference between the earliest and the latest edge. Period jitter can impact the performance of a synchronous system by reducing the timing budget. The variation of clock period from its ideal position may also lead to data setup and hold time violations.

A 100MHz clock signal modulated with 1% up-spread will have a total frequency variation (f) of 1MHz, with a start frequency being 100MHz and stop frequency 101MHz. This corresponds to variation in period from 9.9ns to 10ns. As a result, the ideal spread clock will have peak-to-peak period jitter of 0.1ns (100ps). As the spread amount is increased or the clock frequency increments keeping the spread fixed, the total frequency variation increases proportionally, hence the PJ may violate certain timing parameters.

One must note here that the PJ mentioned here is solely the one introduced due to the spread clock. The device itself may add its own intrinsic jitter, making the total jitter higher than estimated above. The intrinsic jitter of device may be measured by turning off the spread.

b) Long-term jitter (LTJ): LTJ is similar to period jitter but represents the maximum change in a clock's output transition from its ideal position over many cycles. Although it is applicable to a few specific applications, it becomes crucial with spread spectrum signals where the timing edges could be significantly displaced in time from their ideal locations. The best example of a problem with LTJ can be seen on a graphics card driving a display: excessive LTJ may cause the pixel data to be shifted from its desired position over a span of time.

c) Cycle-to-cycle jitter (CTCJ): CTCJ is another jitter type defined as the change in clock's output transition from its corresponding position in the previous cycle. CTCJ is mostly undesirable in communication systems or in ADC circuits where the input signal is sampled at a particular instance and digitized according to the sampled value.

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