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Mask correction feature speeds up IC processing

Posted: 22 Sep 2011 ?? ?Print Version ?Bookmark and Share

Keywords:lithography? source mask optimization? IC manufacturing?

Brion Technologies Inc. has launched its Tachyon Model-Based Sub-Resolution Assist Features (MB-SRAF) for its Tachyon computational lithography platform. According to the company, the assist features allow high-speed, full-chip processing of advanced chip designs with high productivity and low costs. The SRAF also provides a larger process window, giving greater latitude in imaging.

With devices scaling down to the 2x-nm nodes, the traditional rule-based approach for SRAF placement and sizing is becoming complex, especially for 2D layers such as contacts, vias and metals. The industry-wide adoption of freeform illumination enabled by ASML's FlexRay technology and Brion's Tachyon source mask optimization (SMO) software challenges the limitations of rule-based SRAF technology. To realize the benefits in imaging by the FlexRay illuminator and to make the solution robust against all pattern proximities and layout variations, there are many rules governing SRAF shape, size and placement. Development times for rule-based SRAFs are thus increasing dramatically. By contrast, a Tachyon MB-SRAF recipe can be developed and optimized in a fraction of the time and cost.

Tachyon MB-SRAF has overcome compute costs, poor correction quality and the impact to mask costs from the pixelated geometries, Brion stated. It also offers comprehensive design space coverage with embedded conflict resolution, mask rule check compliance and SRAF printability prediction for full-chip implementation. In particular, compute times for Tachyon MB-SRAF have been reduced to enable cost-effective full-chip processing, the company added. It has proven to be a key process window enabler for chipmakers who are developing and producing designs at 2x-nm and below.





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