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Double simulation tool boosts wafer quality

Posted: 23 Sep 2011 ?? ?Print Version ?Bookmark and Share

Keywords:IC manufacturing? wafer quality? photomask? double simulation?

D2S Inc. has unveiled the TrueMask DS that it touts as the industry's first mask-wafer double simulation accelerated platform for R&D exploration, bit-cell design, hot-spot analysis and mask-defect categorization.

"Mask features at below 80nm occur frequently at 20nm logic nodes and below," said Naoya Hayashi, research fellow, Dai Nippon Printing. "Of particular interest are SRAFs and other small features that decorate the mask to improve wafer quality.�Particularly for critical circuits, mask customers are interested in making a balanced tradeoff between wafer quality achievable with complex optical proximity correction (OPC)/inverse lithography technology/source mask optimization and the cost and turnaround time of masks. An interactive mask-wafer double simulation would enable efficient exploration of these tradeoffs for critical circuits."

OPC has been used for years to add SRAFs on photomasks to compensate for the optical effects of sub-wavelength lithography that prevent small features from printing correctly. At the 20nm node and beyond, the shapes of these SRAFs as well as main features must become more complex to produce the desired images with sufficient process window on the wafer. This added data causes mask write-times to skyrocketrequiring necessary engineering tradeoffs between acceptable wafer accuracy and tolerable mask-write times.

In addition, as these assist features shrink to below 80nm, there is no guarantee that they can be reproduced as desired on the photomask. This is due to the combination of short-range blur of the electron beam used to write the masks and the effects from the mask develop, bake and etch processes.�In other words, the very features needed to ensure accurate patterning are now printing inaccurately.

Deploying hardware acceleration, TrueMask DS can produce a double simulation of the mask and wafer for 5 x 5?m (on wafer) areas at interactive speeds. Users can experiment using different variable-shaped beam (VSB) shots to write the masks. Then, users can instantly see the shape of the exposed resist and within seconds see an overlay of the lithography aerial image that would be printed on the wafer.

The TrueMask DS features 0.1nm-resolution mask simulation up to 300 x 300?m (mask dimensions), including overlapping shots and dose modulation. It can perform advanced eBeam modeling with arbitrary point spread functions for exploration and fast, interactive aerial litho simulation from hardware acceleration.





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