A primer on 3D-IC design challenges

Last October 2010, Xilinx announced its use of a 2.5D through-silicon via (TSV) process for their Virtex-7 FPGAs. This was followed by announcements from TSMC, Samsung, Nokia, Micron, and Elpida about using 3D-ICs with TSVs, showing that TSV technology has emerged as a proven and viable technology that offers compelling advantages in power, performance, form factor, and time to market. By making it possible to stack analog, digital, logic, and memory dies at different process nodes, 3D-ICs offer what may be the best alternative to the skyrocketing costs of advanced process nodes.

This article examines the terminology associated with 3D-ICs and reviews what 2.5D is, what 3D is, and what the tradeoffs are. It then introduces some 3D-IC design challenges such as system exploration, floorplanning, analysis, and design for test (DFT), and shows how designs will evolve as 3D-IC goes on to become a necessity for managing power, performance, form factor, and cost goals.

3D-ICs with TSVs
Despite the recent buzz in the industry about 3D technology, the concept of 3D is not so new at all. 3D packaging has been around for years—stacks of die with wirebonds, package-in-package (PiP) design, and package-on-package (PoP) design, to name a few. PoP is a widespread configuration that combines a stack of memories on top of an application processor or digital baseband. Both PiP and PoP assemblies may be categorized as 3D-ICs, but neither offers the performance, power, density, and form factor of true 3D-ICs using TSVs. What is new is the extension of the 3D package concept into the IC side.

One extension is to add a silicon interposer substrate (either passive or active) to provide much finer die-to-die interconnections, thereby increasing performance and reducing power consumption. A silicon interposer includes TSVs, which are vertical electrical connections passing through a silicon die, connecting the upper metal layers to additional back-side metal layers (figure 1). This technique is often referred to as "2.5D" packaging.

A "true" 3D-IC using TSVs involves two or more die connected together using TSVs. For example, consider a scenario in which one die containing TSVs is attached to the system-in-package (SiP) substrate using conventional flip-chip technology. Meanwhile, a second die is attached to the first (figure 2). The 3D-IC shown above is referred to as a back-to-face (B2F) configuration, because the back of the first die is attached to the face of the second die. It is also possible to have back-to-back (B2B) and face-to-face (F2F) configurations, especially when more than two die are stacked in this manner.

Except for memory stacks, it is unusual these days to see more than two layers of dice stacked on top of each other. However, the potential of 3D-IC design is huge and once the technology is mainstream, it will be possible to build complex scenarios (figure 3).

Compared to a wire-bonded SiP (3D package), TSVs offer reduced RLC parasitics, better performance, more power savings, and a denser implementation. Compared to a silicon interposer (2.5D) approach, a vertical "true" 3D die stack offers a higher level of integration, smaller form factor, and a faster design cycle. But a 3D stack raises some additional challenges—including thermal, timing, and power management concerns—which are mitigated in the 2.5D approach. So, deciding between 2.5D and 3D requires making a tradeoff among power, performance, form factor, and cost. It also depends on the applications you are targeting. FPGAs, CPUs, GPUs, gaming, and servers are better suited for 2.5D; low-power applications like smart phones and other wireless applications are better suited for 3D.

Challenges, requirements
While 3D-ICs with TSVs do not require a revolutionary new 3D design system, they do require some new capabilities that need to be added to existing toolsets for digital design, analog/custom design, and IC/package co-design. 3D-ICs require additional components to enable the 3D interconnection (figure 4).