Overcome memory hurdles for next-gen servers

As a new generation of server processors is seen to rise, system designers are now focusing on load-reduced dual inline memory module (LRDIMM) technology and its potential to break the memory capacity and speed barriers in upcoming servers. Designers are compelled to consider LRDIMM technology because it significantly expands servers' memory and storage options, and offers wide array of features and relative ease of design.

LRDIMM is the most recent advancement in DIMMs supporting DDR3 SDRAM main memory. Fully pin-compatible with existing JEDEC-standard DDR3 DIMM sockets, LRDIMM supports increased system memory capacities operating at higher speed than the available registered DIMM (RDIMM) technology. While DDR3 technology is established and has already realized a large degree of acceptance in the server-design community, LRDIMM presents a new set of values in terms of bandwidth, capacity and cost.

In contrast to RDIMM, the previous de facto standard for memory, LRDIMM offers substantially faster operating data rates in the highest-capacity configurations and new features designed to improve testability, usability and memory capacity. Furthermore, LRDIMM does this with a marginal power penalty in high-capacity, multiple-DIMM-per-channel configurations. While RDIMM forces end-users to make tradeoffs between memory capacity and operating speed, and has fallen behind in terms of staying apace with ever-increasing user demands, LRDIMM overcomes these obstacles, enabling higher capacity in systems running at the highest operating speeds.

Buffer at the heart of LRDIMM
At the heart of the LRDIMM technology is the memory buffer, which vendors such as Inphi have pioneered and evolved to meet system designers' steadily increasing demand for speed and capacity. Figure 1 shows a high-level conceptual drawing of an LRDIMM, featuring one memory buffer on the top side of the module and multiple ranks of DRAM mounted on both front and back sides. The memory buffer re-drives all of the data, command, address and clock signals from the host memory controller and provides them to the multiple ranks of DRAM. This isolates the DRAM from the host, reducing the electrical load on any data bit. Reducing the electrical loading in this manner allows a system to operate at a higher speed for a given memory capacity, or to support a larger memory at a given speed.

On existing RDIMM technology, the data bus connects directly to the multiple ranks of DRAM, increasing the electrical load and limiting system speed as the desired capacity increases. LRDIMM precisely addresses these limitations by reducing the electrical loading on the host memory controller. In LRDIMM, the controller communicates only with the memory buffer to which the task of communicating with the DRAM components is offloaded. This allows the controller to be efficient and drive signals to the memory buffer at a higher data rate. Figure 2 shows system-level block diagrams that illustrate how RDIMM and LRDIMM contrast in this regard.