Signal integrity issues at 10 Gbit/sec and beyond

Experienced designers of 10 Gbit/sec (10G) Ethernet, SONET/OTN, Infiniband (QDR/FDR), and Fiber channel (16/8GFC) products well know that the maintenance of signal quality is far more challenging at 10-Gbit/sec speeds than in the 1-to-3 Gbit/sec range. Those who are initiating their first designs in the 10-Gbit/sec realm may have to confront new realities that will dominate signal-quality issues, as backplanes and network interfaces move into that speed range.

There are discontinuities which are encountered, not only at the level of the individual device, but also at the level of the board trace, and these influence both board layout and the choice of substrate materials (such as FR4). A properly shaped, "clean" transmit signal will look very different at the receiver, as an eye pattern shows (figure 1).

Characterizing signal-integrity issues for line cards and backplanes at 10 Gbit/sec and above requires visualizing the design at board level and device level simultaneously (figure 2).

In fact, even though system developers must keep track of the equalization and error-correction capabilities of individual devices used in high-speed designs, printed circuit board (PCB) designers have been called the "gatekeepers" of 10G design methodologies. When the task is considered at both board and device levels at once, a few common sources of potential signal integrity problems emerge:

PCB layout: Characteristics of physical design, such as the use of via stubs, can have a significant impact on the integrity of data channels operating at tens of gigabits per second. AC-coupling difficulties can be aggravated by the scrambling methods used in advanced designs. As standards have shifted from 8B/10B encoding to 66B/64B, such scrambling is an order-of-magnitude more difficult to address.

The combination of poor via layout and AC coupling can lead to significant baseline wander of a signal, which cannot be alleviated through input equalization. Instead, design discipline at both device and board level must be practiced, along with real-time monitoring of eye patterns.

This is not a cause to fear high-speed design. The real-time monitoring of behavior is deterministic, and signals may be monitored using test equipment available at a reasonable cost. But constraints for signal quality must be considered from the early stages of a high-speed design. For example, back drilling of via stubs, isolating traces by spacing them at least three dielectric thicknesses away from each other, and finally, using a large AC-coupling capacitor to pass-through low frequency content.

Plane discontinuities: Discontinuities can be handled through proper termination of signals and a simple, straightforward board layout. The problem arises when discontinuities propagate throughout a single design, through the use of multilayered boards with many via stubs, surface-mount components with multiple vias, and devices of all types (particularly surface-mount) with fast transmission-edge rates. Ground vias should be spaced appropriately to prevent waveguide modes from occurring, due to a large number of vias along signal traces, and sparse allocation of ground vias even in open areas.

Edge rate design techniques: This is an issue related to specific devices used in a design, which can have an impact on board-level layout. Fast output edges and rise times can eliminate or lessen the need for pre-emphasis or de-emphasis, and designs without pre-emphasis or de-emphasis can offer less crosstalk and lower power dissipation. The consideration of edge rates allows us to segue into signal integrity issues more appropriately considered at the device level.