Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Memory/Storage

Benefits of SONOS memory for embedded flash

Posted: 13 Oct 2011 ?? ?Print Version ?Bookmark and Share

Keywords:embedded? non-volatile memory? Embedded flash? Silicon-Oxide-Nitride-Oxide-Silicon? SONOS?

A transmission-electron-microscopy (TEM) cross section of an actual SONOS transistor integrated into 65 nm baseline process is shown in figure 1.The schematic is a SONOS transistor that is fabricated using a typical foundry logic CMOS process flow. The device has salicided gate, source, and drain regions and the gate stack is made up of salicided polysilicon. The embedded SONOS technology typically offers multiple cell options to fit into different application, without compromising reliability. The program speed is 1 to 5 ms and erase speed is 5 to10 ms depending on application options and macro architecture. The same cell can be used for Flash and EEPROM.

SONOS cell reliability
A key requirement for an NVM cell is reliability. The end-of-life (EOL) threshold voltage (Vt) window of a NVM cell is determined by the degradation caused by program/erase cycles (endurance) and Vt decay during storage (data retention). Endurance is typically characterized by cycling a SONOS cell through the required number of program/erase cycles and measuring the shift of program and erase Vts. Retention is characterized by taking the SONOS cell through a fixed number of program/erase cycles and then measuring the change of Vt (program or erase) with time at an elevated temperature. Figure 2 illustrates the typical endurance and retention characteristics.

Figure 2: Endurance (top) and Retention Characteristics (bottom) of 65 nm SONOS FET.

The endurance characteristics show that Vt shift is negligible after 10,000 program/erase cycles at 70C. The retention characteristic shows that the EOL Vt window is significantly larger than the minimum window required for sensing the state of a NVM cell.

65 nm process
The integration scheme includes a dual-gate-oxide process, which enables the chip to be compatible with multiple supply voltages. Cypress recently integrated the embedded SONOS flash technology into UMC's LL65 baseline process, and achieved working silicon on a 576KB flash macro test chip (figure 3). The macro exhibits retention at 150 C after 10,000 cycles.

Figure 3: SONOS eFlash Test Chip.

?First Page?Previous Page 1???2???3?Next Page?Last Page

Article Comments - Benefits of SONOS memory for embedde...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top