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Low-power SoC touts 10.2pJ/cycle at 0.54V

Posted: 10 Oct 2011 ?? ?Print Version ?Bookmark and Share

Keywords:microprocessor SoC? wireless sensor? power consumption?

STMicroelectronics NV and the Microsystems Technology Laboratories (MTL) of Massachusetts Institute of Technology (MIT) have shown the results of an R&D project that target low-power microprocessor technology. According to them, the 32bit microprocessor SoC reduces power consumption to 10.2picojoule (pJ)/cycle at 0.54V, while SRAM memory cells can operate at 0.4V.

"This breakthrough technology can enable the development of an entirely new generation of microprocessors for wireless sensors and implantable medical devices, where minimized power consumption and long battery life are absolutely critical," stated Alessandro Cremonesi, strategy and system technology group VP at ST.

"We are excited that our collaborative project with ST has resulted in an ultra-low-power microprocessor SoC. MIT researchers and ST engineers worked together to develop and implement a number of architectural and circuit technique to reduce power consumption. The energy-efficient processor will enable a number of exciting sensor network applications such as embedded biomedical systems," noted Anantha Chandrakasan, department head of EECS at MIT.

Implemented in ST's 65nm CMOS process, memory-access power consumption is further reduced through small latch-based instruction and data caches at the first level of the hierarchy. Additional features that make the SoC a compact and self-contained system include on-chip ultra low power clock generation and A/D conversion, said the company. It also has a set of peripherals such as timers and serial interfaces that function at the minimum voltage supply.

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