Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

1.5GHz microprocessor cluster targets SoC design

Posted: 11 Oct 2011 ?? ?Print Version ?Bookmark and Share

Keywords:28nm? microprocessor cluster? process technology?

MIPS Technologies Inc. and eSilicon Corp. have unleashed the tapeout of a high-performance, three-way microprocessor cluster on 28nm-SLP process technology. MIPS provided the RTL based on its MIPS32 1074Kf coherent processing system (CPS). eSilicon completed the synthesis and timing-driven layout, optimizing the design to achieve true worst-case performance of 1GHz for the cluster.

"The 1074K CPS provides an ideal high-performance platform for today's SoC designs, with headroom for tomorrow's designs. We worked closely with eSilicon on this project to not only demonstrate the capabilities of the high-performance 1074K CPS in a new low-power process, but also to enable our customers to use the resulting implementation in their SoC designs," noted Gideon Intrater, VP of product marketing and applications, MIPS Technologies.

The typical performance is expected to be about 1.5GHz. To reach the 1GHz target without compromising low power, eSilicon's custom memory team created custom fast cache instances (FCIs) for the L1 caches to replace standard memories that were in the critical path of the design. The 1074Kf CPS is based on the combination of two high-performance technologiescoherent multiprocessing and the superscalar, Out-of-Order (OoO) MIPS32 74K processor core as the base CPU. The 74K core is a multi-issue, 15-stage OoO architecture. It is in production for customers of digital TVs, set-top boxes and some home networking applications. It is broadly used in Internet-connected digital home products, state the company.

"This was an exciting project for our custom IP engineers. Our custom FCIs did the trick in enabling us to meet the fast-approaching shuttle date. Together with the high quality of the MIPS 1074K design, we were able to quickly meet the challenging performance targets in a low-power process," stated Paul Hollingworth, eSilicon VP of strategic marketing. "eSilicon is looking forward to embedding this cluster into SoC designs for our customers to help them achieve a truly compelling combination of high performance, low price and low power."

Customers can either license the 1GHz implementation from eSilicon as is or customized. The cluster has been taped out as a test chip and will be offered as a hard macro core. It includes embedded design-for-test (DFT) and design-for-manufacturing (DFM) features so that it can be dropped into a chip design and used without modification. As part of a full SoC development, it can be further customized and optimized to meet the specific needs of the application.

Wafers are running in GlobalFoundries' Fab 1 in Dresden, Germany, with silicon expected in early 2012.

Article Comments - 1.5GHz microprocessor cluster target...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top