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Price challenges hinder TSV adoption

Posted: 11 Oct 2011 ?? ?Print Version ?Bookmark and Share

Keywords:TSVs? 3D stacks? Wide I/O? DRAM?

In order for chip stacks using high density through-silicon vias (TSVs) to be used in high volume devices, major price adjustments should be done. This is according to Matt Nowak, a senior director of advanced engineering at Qualcomm Inc.

Nowak reviewed progress on technology challenges for TSVs in a keynote address at the International Wafer-level Packaging Conference. In comments after his talk, he said industry debates over prices and business models are the biggest hurdles ahead.

"TSVs are a long way off if we can't solve the price problem," said Nowak. "There's a big gap between price and cost, a large delta" based on uncertainties and risks of a new technology and volume demand for it, he said.

Matt Nowak

Nowak: The Achilles heel [for TSVs] is cost.

Several sources say smartphone mobile applications processors could use TSVs as early as 2014, becoming one of the first high volume applications of the technology. A Wide I/O memory interface in the works at Jedec paired with TSVs aims to be the successor of a low power DDR3 link coming for next-generation mobile processors using a package-on package (PoP) approach.

"LPDDR3 is coming along as the next clear technology for package-on-package devices offering 12.8GB/s, and somewhere beyond that Wide I/O has the potential to intersect the market," said Nowak who oversees work on TSVs at Qualcomm. "Technically Wide I/O could be used by 2014, but there are pricing and business model issues that if they are not settled will make it a moot point," he added.

TSVs promise to raise performance while lowering power and keeping device sizes low for a range of applications including mobile processors.

"The Achilles heel [for TSVs] is cost," Nowak said in his keynote. "Wide I/O DRAM is considerably more expensive than current PoP configurations, and PoP will continue to evolve and maybe find ways to squeeze one more generation out," he said.

Nowak said one industry consortium, the EMC-3D group, recently concluded TSVs will add about $120 additional cost per wafer based on its models of tools now in production. The group claims on its Web site it sees a path to prices coming down to about an extra $150 per wafer.

The lack of clear business models complicates the pricing issue, Nowak said. For example, it's still a matter of debate which parts of the process are done in a wafer fab and which in a packaging house and who will be liable for yields.

"Some companies may act as integrators and take liabilitylikely the model will evolve," he said, noting that some TSV supply chain partnerships already are forming.

Motives and progress
Qualcomm designed a prototype 28nm TSV device in an effort to show both the promise and the problems with the technology.


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