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The move toward 3D chips

Posted: 14 Oct 2011 ?? ?Print Version ?Bookmark and Share

Keywords:3D chips? TSVs? IC manufacturing?

Semiconductor fabrication is moving toward a new trend. Over the next few years, fabrication will be from dice that are planar to multistory structures. Three-dimensional (3D) ICs have undergone over a decade of major semiconductor engineering efforts to make the structures more manufacturable. And by next year although it's already several years behind schedule the chips are ready for commercialization.

Chip makers have spent the past several years perfecting the through-silicon vias (TSVs) that will interconnect 3D ICs. Now that TSVs have been honed for 2D tasks, such as transferring data from the front side of a planar chip to bumps on the flip side, the stage is set for 3D ICs using stacked dice.

Last winter's International Solid-State Circuits Conference featured "almost-3D" chips, such as Samsung Electronics Co.'s much-publicized 1Gbit mobile DRAM (with a planned ramp to 4Gbits by 2013). Samsung's 2.5D technique mates stacked DRAM dice with TSVs and microbumps atop a system-in-package.

Samsung's 1Gbit DRAM

Samsung announced this wide-I/O 1Gbit DRAM for smartphones and tablets at this year's ISSCC. The device uses 3D TSVs mated to microbumps. SOURCE: Samsung

A second major 2.5D success is expected this fall, when Xilinx Inc. promises to deliver a multiFPGA solution using a packaging process that interconnects four side-by-side Virtex-7 FPGAs with microbumps on a silicon interposer. Taiwan Semiconductor Manufacturing Co. is making the silicon interposer, which redistributes the FPGAs' interconnections using TSVs that mate to copper balls on a substrate package using a controlled-collapse chip connection (C4). TSMC promises to make its seminal 2.5D-to-3D transition technology available to its other foundry customers next year.

Samsung's 1Gbit DRAM

Xilinx uses TSVs combined with controlled-collapse chip connection solder bumps to mount four FPGAs on a TSMC-made silicon interposer. SOURCE: Xilinx

The surprise 3D IC announcement for 2011, however, comes from IBM Corp., which recently confided that it was already secretly mass-producing full-fledged 3D ICs on high-volume mobile consumer devices, albeit using low-density TSVs. As a result of the experience it has gained, IBM now claims to have identified the remaining engineering hurdles to 3D and says it expects to surmount them in 2012.

"The era of the one-trick pony is gone," said Bernard Meyerson, vice president of research at IBM. "You are not going to win the 3D performance battle if you rely solely on materials, or chip architecture, or networking, or software and integration. To win at 3D, you need to use all these resources together at the most holistic level possible."


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