The move toward 3D chips(2)

The move toward 3D chips

Last month, IBM announced it had approached 3M about creating a designer material—akin to asking for "a really tall short person," as Meyerson described it—that would solve the last remaining engineering hurdle to 3D ICs: overheating. 3M's job is to create an underfill material that fits between stacked dice and is an electrical insulator (like a dielectric) but is more thermally conductive than silicon (like a metal). 3M promises to have its miracle material ready for commercialization in two years.

"Right now we have trials ongoing, and by 2013 we want to have a formula in place that is ready for widespread commercialization," said Ming Cheng, technical director of 3M's electronics markets materials division.

Some analysts are not convinced the IBM-3M joint development effort will necessarily put the pair ahead in 3D ICs.

"3M is making an underfill material that will address the thermal issues for 3D stacking," said Fran?oise von Trapp, principal analyst for advanced packaging technologies at the MEMS Investor Journal. "While that's definitely one of the remaining limitations needing to be addressed before 3D ICs go to volume production, I don't think anyone believes it's the final key to unlocking the remaining issues for 3D stacks."

3D everywhere
Even IBM's claimed lead in 3D IC production is not without its challengers. In fact, Tezzaron Semiconductor has been offering 3D IC design services for its tungsten TSV process for several years. Tezzaron's FaStack process can create 3D chips from heterogeneous dice on wafers as thin as 12 microns. It features wide I/O for stacked DRAMs with submicron interconnections as dense as 1 million TSVs per square millimeter.

Serial entrepreneur Zvi Or-Bach, a past winner of an EE Times ACE Award for Innovator of the Year, argues that 3D IC designers need to move beyond TSVs to ultrahigh-density monolithic 3D. That's not a surprising view for Or-Bach, whose latest role is president and CEO of IP developer MonolithIC 3D Inc. Startups like BeSang Inc. claim to be fabricating prototypes of TSV-free monolithic 3D memory chips that could debut in 2012.

The state of the art today, however, is 3D chip stacking using TSVs, and every major semiconductor company is working on the technology. "IBM is pushing the envelope, thinking beyond the current frame of things by partnering with 3M. However, every advance made by IBM in 3D will unleash the creativity in competitors like Samsung, Intel and TSMC, all of which have independent development efforts under way for 3D ICs," said market watcher Richard Doherty, director of The Envisioneering Group.

The techniques for making 3D ICs are not new; rather, the current efforts focus on refining them. For instance, many CMOS imagers today use TSVs to bring pixel data from the front to the rear side of their substrate, and the idea of stacking chips itself dates back to early patents issued to transistor pioneer William Shockley circa 1958. Since then, many stacked-die configurations have been used—such as stacking a MEMS sensor atop an ASIC, or a small DRAM atop a processor core—but usually using wirebonding for interconnection.