The move toward 3D chips(3)

Moving from wirebonds to TSVs allows interconnections to be denser. It also it frees designers from the tyranny of the rectangular "farm plot," letting them design chip layouts more like circuit boards. Areas devoid of circuitry could be used for other structures, such as vertical interconnection buses or even chimneys for refrigerant gases. Heterogeneous 3-D stacked dice also offer a new level of integration, as whole systems can be combined into a single silicon brick.

"The most important thing that 3D ICs bring is an opportunity to get away from the farm analogy, where every chip is divided up into adjoining rectangular neighborhoods that are fully populated," said Doherty. "Instead of trying to use up all of the real estate on a chip, 3D chip designers are going to start cutting out squares, triangles and circles [from dice] for vertical interconnect and to carry away heat.

"A lot of new ideas for chip design are being made possible by 3-D. Designers are going to have to think differently, since they can now mix their CPU, memory and I/O functions in novel ways that couldn't be done when everything had to fit side-by-side on one postage stamp."

The various semiconductor associations are all undertaking standards efforts for 3D techniques. Semiconductor Equipment and Materials International has four groups working on 3D IC standards. Its Three-Dimensional Stacked Integrated Circuits Standards Committee includes SEMI members Globalfoundries, Hewlett-Packard, IBM, Intel, Samsung and United Microelectronics Corp., as well as Amkor, ASE, Europe's Interuniversity Microelectronics Center (Imec), Asia's Industrial Technology Research Institute (ITRI), Olympus, Qualcomm, Semilab, Tokyo Electron and Xilinx.

Sematech, for its part, has established a 3D Design Enablement Center. Participants include Altera, Analog Devices, LSI, ON Semiconductor and Qualcomm. Sematech also operates a 300-mm 3-D IC pilot line at the University of Albany's College of Nanoscale Science and Engineering in New York state.

Imec is working with Cascade Microtech Inc. in the testing and characterization of 3D ICs. And German research institute Fraunhofer IZM says it will be able to integrate processor, memory, logic, analog, MEMS and RF chips into monolithic 3D ICs by 2014.

ITRI, based in Taiwan, sponsors a 3D IC consortium that today has more than 20 members. Many of those participants are promising end-to-end 3-D IC foundry services starting as early as next year.

In September, at the 3D IC Technology Forum held during Semicon Taiwan, Intel was reported to be working on stacked-die 3D ICs (not to be confused with its FinFET trigate transistors, which are not intended for 3D ICs). Also at Semicon, Elpida Memory was reported to have made progress with Powertech Technology and UMC on a 2Gbit DRAM that uses stacked DDR3 dice linked by high-density TSVs.

The Joint Electron Device Engineering Council (JEDEC) is pioneering a Wide I/O standard for 3D ICs that's due by year's end. The JEDEC spec will support 512bit-wide interfaces.

France's CEA-Leti is working with STMicroelectronics and silicon interposer maker Shinko Electric Industries Co. to smooth the 2.5D to 3D IC transition. The group is prototyping devices now at a 300mm wafer fabrication facility and promises commercial designs as early as 2012.

Longer-range efforts are under way in Europe's CMOSAIC program to find novel methods of cooling monolithic 3D chip stacks beyond 2013. The four-year project involves IBM Zurich, ?cole Polytechnique Fédérale de Lausanne and the Swiss Federal Institute of Technology Zurich.

- R. Colin Johnson
?? EE Times U.S.