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Recent developments in 3D integration

Posted: 19 Oct 2011 ?? ?Print Version ?Bookmark and Share

Keywords:through-silicon via? mechanically flexible interconnect? 3D?

One of the key elements in the evolving science of 3-dimensional (3D) packaging is the through-silicon via (TSV). Already in production, TSVs are holes etched vertically through the thickness of the silicon, usually at the wafer level. The holes are then plated with copper to provide conductivity and to provide a simple means of stacking chips.

A memory chip, for example, can be stacked on top of a processor chip. The bottom ends of the TSVs in the memory chip can be connected to the processor by solder bumps. This arrangement means that regions of the two chips that frequently transmit data can be placed at the two ends of the TSVs for very fast operating speed. Speed is also increased because TSVs do away with the much longer wirebondss that have been used to connect stacked chips.

Much of the research into TSVs and technologies based on TSVs has taken place in Georgia Tech's Integrated 3D Systems Group. Prof. Muhannad Bakir notes that current technology permits the creation of up to 10,000 TSVs per square centimeter.

One unique application for TSVs is in the development of silicon interposers that can be placed, for example, between a die and an organic substrate. A silicon interposer has fine pitch interconnects on its top surface to connect with and redistribute signals from the die above. Currently the connection is by means of microbumps. The silicon interposer's interconnects redistribute signals to TSVs running downward through the interposer and connecting with the organic substrate.

As you might expect, there is a significant size difference between the TSVs in the chip above and the TSVs in the silicon interposer. Chip TSVs are perhaps a few microns in diameter, while those in the silicon interposer tend to have diameters measured in tens of microns. The business of silicon interposers is still in its infancy: a few products have been marketed, and development companies are advertising their ability to make interposers for specific applications.

Silicon interposers having dense wires also offer an opportunity to cut costs while improving product reliability. Xilinx used this route in 2010 to improve the die-to-die bandwidth per watt by a factor of 100 in its 28nm 7 series FPGAs. Very large FPGA chips are difficult to fabricate with reasonable yield. So Xilinx used four smaller FPGAs to replace a single large FPGA, and placed the four smaller chips on a silicon interposer. This method also provides the advantage that the assembly can be tested after the placement of each of the smaller die.

One area of manufacturing where TSVs and silicon interposers may be especially useful is MEMS. The reason has to do partly with the history of development in the MEMS industry. A MEMS device has a sensor of some type that is connected to and sends its data to a processor. Conventionally, these two chips are placed side by side on a printed circuit board and connected by wires. But taking an existing pair of MEMS chips and placing the sensor on top of the processor runs into the problem that each chip has been developed in isolation, for its specific application, Since MEMS devices are tending toward higher performance and higher speed, redesigning chips to include TSVs, perhaps with silicon interposers as well, could be a good move.

The role of MFIs
One of the potential problems in any IC package is the reaction of the package over the long term to thermo-mechanical stress. For example, flip chips use underfill to isolate solder bumps and contain thermo-mechanical stress that could ultimately break the die. But underfill itself can cause problems: it may interfere with RF transmission at high frequencies, it can interfere with the functioning of MEMS structures, and it may not adequately protect the die from thermo-mechanical stresses. In one study, the performance of a MEMS device was altered by up to 37% by thermo-mechanical stress.

 MEMS chip

Figure 1: Diagram of a MEMS chip with three possible sensor types, connected to the CMOS processor below by TSVs and MFIs.


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