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IP core implements 3D graphics in SoC design

Posted: 17 Oct 2011 ?? ?Print Version ?Bookmark and Share

Keywords:IP core? 3D graphics? FPGA? SoC design?

Xylon Corp. LLC has released a new version of its logi3D Scalable 3D Graphics Accelerator IP core that is intended for the Xilinx Zynq-7000 Extensible Processing Platform (EPP). It enables designers to add striking 2D and 3D graphics, including advanced GUI to their EPP SoC designs.

According to the company, the high performing 3D GPU can be integrated with other soft IP cores in the Zynq-7000 EPP's programmable logic fabric. It can also be interfaced with an industry-standard ARM dual-core CortexT-A9 MPCore available on the same chip, added Xylon. Due to its AMBA AXI4 compliance, the logi3D IP core can also be used in Xilinx 7 Series and other FPGA families as a graphics coprocessor in various ASSP+FPGA combinations.

The logi3D IP is carefully partitioned between hardware and software to assure the highest performances and optimal use of FPGA resources while the rendering engine works fully in the on-chip programmable logic. Special care has been taken to assure many free programmable logic resources for other IP cores are used alongside logi3D IP core in the same Zynq-7000 EPP SoC. The programmability allows for future extensions of the logi3D functionality and the design of graphics solutions customized at the hardware and software level.

To enable early development and demonstrate the IP core before implemention in Zynq-7000 EPP devices, Xylon has designed the ASSP+FPGA-based logiGPU Graphics Demonstration Kit. It combines an ARM Cortex-A8 CPU and Xilinx Spartan-6 FPGA, and runs on Linux OS. The kit emulates future logicBRICKS graphics subsystems implemented in the Xilinx Zynq-7000 EPP, and provides immediate design of 3D graphics.

The logi3D is designed to support the OpenGL ES 1.1 API. Linux is the only supported OS, with compatibility for others planned for next year. The firmware works with ARM processors and can be re-compiled for different CPUs. The assembly code acceleration can be used with ARM processors supported by ARM NEON coprocessor.

The IP core is compatible with the Xilinx Platform Studio and EDK integrated software development tools. Designers can set up the IP core through a GUI, optimize feature sets and control the use of programmable logic resources, and implement Xilinx SoC in a drag and drop fashion.

The logi3D IP core is available as encrypted VHDL source and VHDL source code formats for immediate purchase from Xylon. License fees offered through Xylon's Low-Volume IP Program (LVIP) start at less than $9,900.





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