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Overcome challenges of ASIC/SoC prototyping with FPGAs

Posted: 24 Oct 2011 ?? ?Print Version ?Bookmark and Share

Keywords:SoC? ASIC? ASSP? FPGA? prototype?

The Verification Module is touted to address this limitation by enabling multiFPGA debug. For an Altera-based prototyping system you would use an S4 VM; for Xilinx-based FPGAs you would use V6 VM. The S4 VM is based on a Stratix 4 FPGA and the V6 VM is based on a Xilinx Virtex 6 FPGA. The VMs can be used to debug any number of FPGAs available on a given prototyping system, including a single FPGA. The VM technology allows users to set various trigger conditions on each FPGA. The trigger conditions are set in the SignalTap (Altera) or ChipScope (Xilinx) debug settings menu either on a single or multiple probes pre-defined and available for debug session. Likewise you can set trigger conditions on additional FPGAs of interest (all FPGAs if needed) available on the board. If S1, S2 ... Sn correspond to trigger condition for each FPGA, where n is the number of FPGAs selected for debug, then the master trigger condition, say 'S', would be a Boolean product of each of the individual trigger conditions. S=S1.S2.S3 ...Sn. It may be noted that S1 or S2 ... etc. corresponds to Boolean product of debug probe logic values of the design for a given FPGA.

High speed data transfer: In prototyping, it is often necessary to transfer large amounts of data between the design and the verification environment. This data could be design data that is stored in the FPGA memory or prototype board memory as an image file. Or it could be data captured from a debug session in the form of a VCD file. The data size can sometimes run into gigabytes. To efficiently manage such large amounts of data you need two capabilities. First, you need to have high speed ports that support protocols such as PCIe with multiple lanes that can quickly transfer large amounts of data, for example, x4 PCIe Gen 2 can provide a raw data bandwidth of up to 20 Gigabits (or 2.5GB) per second of data. Second, you need the ability to communicate with the design from the computer verification environment through high level commands such transactors or simple C-API calls. Transaction level communication is efficient and when implemented as SCE-MI (Simulation Co Emulation Modeling Interface) interface, it is portable across multiple projects and prototyping systems. S2C prototyping systems allow designs to communicate with verification environment via C-API calls and SCE-MI based TLM interface.

Reference designs enable quicker implementation: Designs that need to interface to high speed memories such as DDR3 memory (that potentially run over GHz speed) or PCIe Gen 3 or USB 3.0 pose additional challenges in implementing and verifying the prototype design. One is the sheer functional complexity. Another is that to comply with the protocol specs the timing requirements are stringent and require the system to interface with high speed devices. For example, USB 3.0 implemented in 'super-speed' mode runs up to 5Gbit/s, while an x4 PCIe Gen3 interface would need to run at about 32Gbit/s bandwidth. In each of the designs mentioned above, whether you are implementing a controller or PHY, a working design will helps users go a long way. This often serves as a starting point for the designer to develop their own implementation. For example, if you are a developing a PCIe controller, then you could run the reference design and make sure it meets both functional and timing protocols. Later, as you develop your own controller design, you can replace the controller in the reference design with the design in progress and validate for correct behavior, without changing the rest of the verification environment. This makes it much easier to start with a known working reference design and develop and debug your own design. S2C offers a number of 'Prototype Ready Reference Designs' that allows user to quickly begin with a known working verification environment and plug in user's design. This allows user to compare and contrast a working design with a design in progress making debug an easier process.

In addition to Reference Design it is important to have a library of daughter cards that can be used to interface with other devices and validate in the context of a system. These daughter cards may contain third party IPs or standard bus interfaces such as PCIe or GbE and so on.

Debug the design not the prototype board: Regardless of whether you build the prototyping system yourself, or you acquire it from a prototyping vendor, one thing is obvious C you want to spend the least amount of your time in debugging the prototyping board. After all, your goal is to debug your design and not the prototype board. Consider a prototyping system with quad Stratix 4 SE820 device with the F1760 package. The total number of pins, including power and ground, on such boards can be close to 8,000. In order to make sure that the pin connectivity is correct and all signals in the prototyping system function properly, it is critical to have comprehensive self-tests that identify and pin-point the sources of any problems. More importantly, these tests must be easy to run, have short run-times, and provide detailed yet easy-to-understand results. At times, when you suspect the board could be a potential problem, such self-tests will be critical. All S2C prototyping systems come with comprehensive self-tests that allow you to verify I/O pins, clock pins, memory interface and all other signals.

Advances in process technologies have made it feasible to implement very complex capabilities and offer a number of functions in SoC/ASIC/ASSP devices.

Software content continues to dominate and plays a key differentiating role among similar devices. In order to ensure that the designs are thoroughly verified and the software developed to match the desired functional behavior, it is critical to create prototypes of these designs.

Due to their low cost, high performance, and easy deployment, FPGA-based prototyping serves as the ideal pre-silicon platform choice for verification and software development. S2C offers a number of capabilities C debug visibility, multiFPGA debug, high speed data transfer, prototype ready reference designs, and a library of daughter cards C that makes S0C verification and software development an easier and faster process.

About the author
Ashok Kulkarni is the Director of Applications Engineering at S2C Inc. His twenty years of experience includes both semiconductor and EDA industry in ASIC design, Applications Support, ASIC Consulting and Technical Marketing.

Ashok has worked for Synopsys, Cadence, Mentor Graphics, Synplicity, Quickturn and Semi-Custom Logic in various roles. He holds a MSEE from Louisiana State University and an MSEE from Bombay University.

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