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Arasan demonstrates first UFS 1.0 Link Layer IP, HDP

Posted: 26 Oct 2011 ?? ?Print Version ?Bookmark and Share

Keywords:link layer IP? FPGA? HDP systems?

Total IP Solutions provider Arasan Chip Systems Inc. has demonstrated its UFS Link Layer IP, as well as the UFS Hardware Development Platform (HDP) in the Mobile Memory Workshop hosted by TSIA and JEDEC in Hsinchu, Taiwan. The company also demonstrated UniPro on an FPGA, which runs at 1.25Gbit/s (full Gear 1 speed) on a Linux system during the workshop. UniPro is UFS 1.0 compliant.

Arasan's UFS UniPro IP, based on its MIPI UniPro IP certified by UNH Lab, provides the link layer between the PHY and the protocol and application layers in UFS's layered architecture for next generation high speed and high capacity mobile storage. Designed to be independent of the PHY layer, MIPI UniPro is a layered protocol for interconnecting devices and components within mobile systems such as cellular phones, handheld computers, digital cameras and multimedia devices. UFS adopted MIPI UniPro to enable mobile devices such as smartphone and UFS mobile storage devices to utilize UFS PHY layer (i.e. M-PHY) to exchange data at high data rates, with low pin counts and at low energy per transferred bit.

With Arasan's UFS Link Layer installed on two FPGA-based HDP systems (one source and one device) next to each other, Arasan demonstrated the data transfer at 1.25Gbit/s between the source and the destination. With UFS UniPro in an FPGA as the heart of the system, the HDP is designed to accelerate hardware development, software development and compliance testing.

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