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Perform assertion-based verification in mixed-signal design

Posted: 03 Nov 2011 ?? ?Print Version ?Bookmark and Share

Keywords:Assertion-based verification? Property Specification Language?

Assertion-based verification (ABV) is a powerful verification approach that has been proven to help digital IC architects, designers, and verification engineers enhance design quality and minimize time to market. However, ABV has rarely been applied to analog/mixed-signal verification. This article looks at challenges in analog/mixed-signal verification, evaluates how the ABV concept can address some of those challenges, and shows how languages such as Property Specification Language (PSL) and SystemVerilog Assertions (SVA) can be used to write complex analog/mixed-signal assertions.

Assertions, by definition, capture the intended behavior of a design. In verification terminology, ABV can be positioned both as a white-box and a black-box approach in that the user can create properties (or asserted behaviors) that can monitor the design deep within the hierarchy, reaching the internals of the design blocks as well as the interfaces of the design blocks.

Assertions are written both during development of the design and the verification environment. Both designers and verification engineers can consequently be involved in identifying requirements and capturing them as assertions.

Mixed-signal assertions
As design complexity increases, the verification tasks around an analog/mixed-signal (AMS) system become more and more difficult to plan and execute. Some of these fundamental difficulties are:

There is no consistent language or methodology across the complete spectrum of discrete event-driven systems, mixed-signal systems, and continuous time-varying systems to express the verification intent in the form of assertions.

Since no such standard methodology exists, how does information expressed by one group of design or verification engineers in the AMS domain flow to another group, or from one level of design abstraction to another?

In the absence of a standard language and methodology to apply verification to a mixed-signal system in its entirety, how can a verification plan include testing AMS blocks that were tested in isolation in the context of the complete system? This challenge includes verifying aspects such as power sequences, current leakages, and noise figures from the AMS blocks as part of a full-system verification.

The availability of formal property specification languages, with their well-defined set of semantics, has benefited the digital design and verification communities for some time, and in view of the challenges mentioned above, it is natural to attempt to apply the same or similar concepts to the AMS design and verification domains as well. It is with this goal that we show how the standard PSL and SVA languages can be used to extend assertion-based verification to the AMS domains.

Checks and measures in analog
In the analog verification domain, the idea of developing a specification that drives the need for defining assertions is not a common notion. Nevertheless, analog designers and verification engineers do set custom characterization checks to specify the safe operating conditions for the devices that comprise a circuit. In the Cadence Virtuoso Multi-Mode Simulation environment, for example, this is done by adding a special assert device to the circuit and by associating a checklimit analysis to verify if the device-level conditions specified by the user have been satisfied during the course of a simulation that the checklimit analysis corresponds to.

While the application of the assert device along with checklimit analyses is useful to verify the device-level characteristics, there is currently no way to set up and verify more complex circuit conditions that AMS verification tasks encounter. Some of these challenging operations include the ability to predicate assertions on some time-varying circuit characteristics, or the ability to check temporal properties of a circuit at intervals determined by complex clocking conditions.

Moreover, the current use model of using assert and checklimit creates an isolated solutionDthe methodology only applies to pure analog or mixed-signal applications, and it neither leverages nor makes itself visible to the much broader digital verification methodologies that currently exist.

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