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Address challenges in 40G/100G SerDes design, implementation

Posted: 17 Nov 2011 ?? ?Print Version ?Bookmark and Share

Keywords:SerDes? bit-error-rates? Phase-Loop Lock? 40G/100G?

The increasing requirement for higher bandwidth continues to fuel development and demand for 40G and 100G systems. Example consumer applications include YouTube, Facebook, smart phones, and IP-TV. Governmental and business demands compound the urgency with a variety of complex data intensive solutions including weather prediction, financial analysis, genomics research, and design simulation. Further, the rapid emergence of cloud computing for both personal and business use adds additional challenges for high-volume, high complexity data transmission.

To implement these link speeds, SerDes devices must meet tighter performance specifications, with extremely high speeds running at extremely low bit-error-rates (BER). As BER trends lower, the quality of the clock source becomes critical, because the random sources of phase jitter are multiplied by scalar factors (which can exceed 16) for the purpose of link timing closure. Thus, to a large degree, the quality and performance of the link depends on the Phase-Loop Lock (PLL) circuit in the SerDes. To meet the extremely low BER specifications of 10-12 and 10-15, the PLL must exhibit ultra-low jitter, on the order of sub-600fs.

Advanced standards
System requirements for SerDes have become increasingly demanding due to link speeds and new standards, yet 40G/100G transmissions must retain backwards compatibility. As the dominant standard for wireline communications, high-speed Internet builds on the ubiquity of the 10Gbit/s serial Ethernet standard (10G Base-KR, XAUI, RXAUI). The new 40G/100G Ethernet standard leverages the existing 10Gbit/s standard to provide four to ten times the bandwidth. By using a multilane approach, systems designers achieve much higher aggregate data rates than the fundamental electrical line rate. The XLAUI standard (40G Ethernet) achieves 40Gbit/s with four 10.3125Gbit/s lanes while CAUI (100G Ethernet) reaches 10Gbit/s with ten lanes of 10.3125Gbit/s.

Both the 40G XLAUI and 100G CAUI standards retain the Media Access Control (MAC) frame architecture and link encoding (64b/66b) used in 10Gbit/s systems. This minimizes the impact of upgrading systems from 10Gbit/s to 40 or 100Gbit/s, respectively. This explosive growth in demand has stressed enterprises, data centers, and core networking areas the most. These network elements are leading the early adoption of 40G/100G technology.

The next generation of high-speed I/O standards for networks, computer I/O buses, and storage area networks supports these projected bandwidth requirements. Currently, 5 to 6Gbit/s typifies current high-speed transceiver data rates and supports the following standards: PCIe Gen 1 and Gen2; SATA-3; Optical Internetworking Forum (OIF) CEI-6G and CEI-11G electrical standards; and Interlaken.

By contrast, the new 40G/100G Ethernet protocols rely on 8 to 11Gbit/s transceiver rates and the aforementioned multilane architecture. The SerDes Framer Interface (SFI) standard SFI-S, based on the same electrical standards as Interlaken, also reaches 100Gbit/s to support 100G optical networks. The PCIe Gen3 computer I/O bus specification uses the slower rate of 8Gbit/s, but defines x1, x2, x4, x8, x12 and x16 configurations.

Using the PCIe standard, designers can utilize the configurations to address a wide variety of system requirements as needed by individual designs. Even as the industry begins to migrate to 40G/100G, system architects are already anticipating 25Gbit/s transceiver rates and beyond. Figure 1 charts bit rates since 1995 and projects growth along the same line to 2015.

Figure 1: Map of I/O bit rates 1995 to 2015.

PLL, transmitter and receiver design
There are a variety of techniques that can be used to design the critical SerDes circuits. A good transmitter will be compliant to the standards C offering a wide swing range, robust ESD, accurate termination and equalization, and exceeding the return loss. The transmitter will typically be a source of deterministic jitter (DJ) through its power supply noise rejection characteristics. Thus having good local decoupling is critical.

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