Altera initiates OpenCL program for FPGAs

Developed by The Khronos Group, the OpenCL standard is an open, royalty-free standard that supports cross-platform, parallel programming of heterogeneous systems. As a standard parallel language, the standard allows programmers to use a familiar C-based language to develop code across platforms, from CPUs to GPUs, and now expanding to FPGAs.

Altera's OpenCL program combines the parallel performance capability of FPGAs with the OpenCL standard to enable powerful system acceleration. According the company, this heterogeneous system (CPU plus FPGA using the OpenCL standard) also has a significant time-to-market advantage compared to traditional FPGA development using lower level hardware description languages (HDLs) such as Verilog or VHDL.

Through its OpenCL program, Altera has engaged with multiple customers and expanded its university program to support the OpenCL standard for FPGA development in academia, and is actively contributing to the evolution of the OpenCL standard based on customer feedback. Early results of customer evaluations show a 35X performance increase compared to multicore CPU solutions, and a 50 percent reduction in development time compared to HDL-developed FPGA solutions, Altera said.

By adopting a heterogeneous architecture with OpenCL, system architects can maximize performance of algorithmic-intensive portions of their design while also achieving fast time-to-market. Target applications for the standard range from high-performance computing, including climate and financial modeling, to advanced radar systems, medical imaging, and video encoding and processing—any system that requires fast computations that can be parallelized.

The OpenCL standard offers a natural separation between "host" code—pure software, written in standard C/C++, that can be executed on any type of microprocessor—and the "kernel" code, written in OpenCL C, that runs on the accelerator. By profiling their algorithms, system architects can choose which functions to accelerate as kernels in the FPGA device to improve system performance. Multiple kernels can operate in parallel to further speed up processing. The host communicates with the accelerator device via a set of library routines with a minimal set of extensions that allow programmers to specify parallelism and memory hierarchy for the most computationally intensive portions of the code.

"The OpenCL standard enables designers to accelerate their designs and improve their productivity by taking advantage of parallel architectures within the C programming environment," said Udi Landen, vice president of software and IP engineering at Altera. "We have been actively engaged in OpenCL development for years, and are now collaborating with the industry consortium, customers' system architects, and academia to drive FPGA support in the OpenCL standard," Landen added.