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Designing 3D-ICs (Part 2)

Posted: 08 Dec 2011 ?? ?Print Version ?Bookmark and Share

Keywords:physical editing? schematic capture? 3D-IC?

Part 1 of this series talked about the various pieces of the system and looked in depth at the process. Part 2 will look at the other pieces of the system.

The memory design follows a similar flow to the processor, but instead of the primary design entry being Verilog, it is schematic captured. The schematic entry tool we use here is the Micro Magic SUE editor. It is closely tied to the MAX-3D physical editor and has data path compilation capabilities that are handy for the highly bit slice oriented design of a memory. The Micro Magic tools, like the Magma tools, use TCL extensively. In fact, much of Micro Magic's tool set is written in TCL, and thus is very open to adaptation. The designer can use the DPC tool, which extends from the schematic editor, to do the placement and get early estimates of the delays and physical size. Much of memory design consists of fitting together puzzle pieces in an optimal way. The memory cell itself sets wordline and bitline pitch; these in turn dictate sense amplifier and wordline driver pitches, and from here the pitch of the data path elements is set as well. Timing generators and state machines are often complicated, and need to fit into very specific areas to satisfy time of flight constraints and circuit delay matching. It can be difficult to express physical constraints to a layout engineer, so the designer is deprived of the layout engineer's insight into the issues and knowledge of alternate implementations that might work better. In our experience, all too often a block is designed in such a way that the layout engineer must struggle to make things fit. Good interaction between designer and the layout engineer is absolutely essential, otherwise the design ends up much less than optimal. The tight coupling of the SUE editor to the MAX-3D physical editor allows information to pass effortlessly between the designer and the layout engineer. This saves a significant amount of time.

3D physical editing
In 3D design, physical editing is a very big deal. The MAX-3D physical editor is a true 3D editor that allows differing technology files to coexist in the editing environment. We can edit 2D layers or cut and paste across different layers in 3D. The power of this tool becomes obvious when doing real 3D design editing. With 2D tools, simply moving a 3D connection requires separate editing in different tool sessions and data mapping and transfers and external DRC/LVS checking. The MAX-3D tool loads all layers at once and incorporates basic DRC and LVS functions; moreover, the 3D stackup itself is displayed in a direct manner.

Another vital element in 3D design is layer directions. Sometimes connections are face to face, other times face to back, or even back to back. In a stack with several different layers there can be dozens if not hundreds of possibilities. Using 2D tools makes 3D designs difficult and scary; good 3D tools keep track of the layers and understand the 3D connections.

Process separation
Getting back to our 3D memory device, we need to design and lay out two different types of layers for our 3D DRAM. Tezzaron 3D memories use two different types of wafers, constructed with two different process technologies and actually built by two different manufacturers. This process separation enables extraordinary levels of optimization, yielding DRAM with low power, high density, and near SRAM like performance. At the same scale of manufacturing it also allows lower cost, due to higher array utilization and better yields, but that discussion is for another article.The bottom layer of the memory stack is the controller, a logic process technology wafer. This contains the sense amplifiers, I/O interface circuits, test and repair circuits C basically, everything in the memory other than the bit cells and the sub-wordline drivers. Using the logic process to build this layer produces smaller, more compact layouts, much higher performance, and perhaps lower operating voltage.

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