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JEDEC to release 3D IC standard

Posted: 21 Dec 2011 ?? ?Print Version ?Bookmark and Share

Keywords:TSV? LPDDR2? WideIO standard?

Early this year, JEDEC announced that it will release a broad set of 3D IC standards development. The standards developer is now set to release what it touts as the first 3D IC interface standard, which will be out in late December of this year or some time in January 2012.

At the GSA 3D IC task group meeting held earlier this week, Intel Corp.'s Ken Shoemaker presented more details of the WideIO Memories where more details of the electrical and mechanical interface were shared.

JEDEC has a head start in releasing 3D IC standardsits standard for reliability of 3D chip stack with through-silicon-via (TSV), JEP158, was released in November 2009. With the soon to be released WideIO standard, it appears it is maintaining that lead, for now among the standards generation efforts of SEMI, Sematech and Si2.

The industry consensus is that LPDDR2 will run out of bandwidth before WideIO memories are commercially available. LPDDR3 (which is a linear evolution of LPDDR2) is expected to fill this gap by supporting higher operating frequencies while maintaining power efficiencies of LPDDR2. The 800MHz LPDDR3 will feature 50 percent more bandwidth than a 533MHz LPDRR2 while retaining the equivalent pin count as LPDRR2.

WideIO positioning

Figure 1: WideIO positioning (Source: Sophie Dumas, ST-Ericsson, Mobile Memory Forum, June 2011)

Developed by JEDEC task group JC42.6 which began its work in December 2008, WideIO is explicitly a 3D standard for now (2.5D interface is on the future development roadmap) combining logic and DRAM in the same package to reduce interconnect capacitance. The soon-to-be released specification calls for a maximum 4-dice stack of memory cube that can interface to a logic SoC with a maximum target package size of 10x10x1mm.

JC42.6 for WideIO specifies the logic to memory interface (LMI) leveraging the work of two JEDEC committeesJC42.6 (Low Power DRAMs) and JC11 which has a long-standing in mechanical standardization of chip packages. The mechanical interface between memory logic and memory has been generically named as Micro Pillar Gate Array (MPGA).

The interconnect method between logic and memory is not specified and can be micro bumps, micro pillars, etc. The standard also specifies boundary scan to test interconnect continuity, post-assembly direct-access memory test, location of thermal sensors in the memory dice, and the exact mechanical layout of the chip-to-chip interface.

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