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Prepping Ethernet for new prioritization, timing tasks

Posted: 05 Jan 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Ethernet? switches? TDM? MLPS?

The type of software-enabled SLA dial-up the enterprise customer will see for multiprovider OAM is the same model that can be expected in prioritizing traffic. Some enterprise customers will not want to choose a traffic-management model, but opt for best available given chosen SLAs and traffic conditions. Others may want to choose their buffering and packet-prioritization algorithms enabled at the demarcation port. Similarly, a majority of enterprise customers will not want to explicitly choose their ring-restoration or fault-recovery mechanisms if there is a network fault, they will simply seek a Sonet-like restoration time of less than 50 ms. But there may be cases where an enterprise customer wants the Hybrid NID to specify recovery mechanisms (if available from the provider), and to enable those requests via software.

As devices at the network edge adopt more complex security environments that combine bulk encryption, authentication, and other services, the hardware at the network edge should be able to scale to handle a mix of IPsec, MACsec, Public Key Infrastructure, and similar security domains.

As the public-private demarcation point adopts complex mixes of Layer 2 bridging/switching and Layer 3 routing, the enterprise customer may demand ad hoc mixes of MPLS and bridging at the edge of the network, including full MPLS pushed to the enterprise network edge. This requires that a transparent mix of Ethernet with IP/MPLS and MPLS-TP services be provided for any label switching and bridging contingencies that might be encountered.

New generations of switch, MAC, and physical-layer chips for Ethernet, such as Vitesse Semiconductor Corp.'s Serval switch, address the new QoS and timing demands. Serval integrates a MIPS processor to support advanced features such as multiple packet queuing policies, and has an on-board ternary CAM memory to aid in Layer 3 classification. As a result the switch can support any combination of MPLS, MPLS-TP, and traditional bridging.

The core Serval architecture supports 8 QoS classes with up to 2,616 queues. On-chip shared buffer memory uses per-color watermarks (green/yellow/red frames and bytes) to set up dedicated areas in memory for different service classes. The hierarchical QoS algorithms support Weighted Random Early Detect, dual leaky bucket traffic shaping, per-priority flow control, and per-service queuing, meeting all Metro Ethernet Forum guides for Service Level Agreements.

Serval's hardware-based OAM supports IEEE 802.3, 802.1ag, MEF-16, and Y.1731, including the latter's up and down Maintenance Entity End Points, or MEPs. This offers full support for OAM at port, service, and path level. The switch supports 12 all-hardware port MEPs, and 64 all-hardware path and service MEPs.

While MEP support was present on Caracal, the Serval switch offers additional OAM support for continuity checks, loss measurement, delay measurement, and loopback, all in multiple modes. Generation of OAM frames takes place entirely through hardware, and resultant frames are sent to the switch's on-chip 416MHz MIPS processor. Including the frame-forwarding RISC core on the switch chip itself is another area where Serval provides a unique advantage in saving real estate. This MIPS processor has itself been upgraded with new support for PCI Express, DDR2 and DDR3 SDRAM interfaces, and the Vitesse Register Access Protocol for inband read and write.

Network timing is critically important at the edge of the network, for insuring consistent and accurate SLAs. Serval supports 1588v2 in one- and two-step modes, including the multiple clock types defined in 1588v2, including master clock, slave clock, boundary clock, peer-to-peer transparent clock, and end-to-end transparent clock. The on-chip MIPS core runs point-to-point protocol and filtering software.

About the author
Uday Mudoi, director of product marketing at Vitesse, has more than 16 years of experience in the communications and semiconductor industries. Mudol started his career at Siemens and joined Vitesse in 2000. His experience in networking and communications includes a variety of technology areas including Enterprise solutions such as network processors, Ethernet switches, green technology, Carrier Ethernet, and modem chipsets. He holds a Bachelor of Science degree in Electrical Engineering from the Indian Institute of Technology, Kharagpur, and a Master's degree in Computer Science from North Carolina State University. He also received an MBA from Columbia University.

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