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FPGAs in the era of silicon convergence

Posted: 03 Jan 2012 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? process manufacturing? production nodes?

Semiconductor technology has entered a new period in its evolution. The expectation is gone that every 18 months would bring a new process node with greater transistor density, greater speed and lower power. Today at 28nm we see chips with the capacity to implement entire systems, save for the power components and commodity memory. But process engineers, circuit designers, chip designers and architects must all work together to find improvements in system performance and energy efficiency in an increasingly difficult technology.

This change is having profound effects all across the semiconductor industry, driving up engineering costs, increasing risks, and pushing customer-specific systems-on-chip (SoCs) beyond the reach of most systems developers. It is also changing the nature of FPGA companies and their relationships with their customers.

FPGAs are among the first designs to use and to stress-test a new process generation. For example, Altera Corp. began shipping some of the powerful and complex members of its tailored 28nm FPGA family, built in TSMC's highest-performance 28nm process, in early 2011. Doing this required an intimate relationship with our foundry, based on the accumulated experience of working together at ten earlier production nodes. Both parties had to cooperate in process engineering, transistor design and circuit design in order to achieve shippable yields on FPGAs that actually deliver the inherent benefits of the new process early in the process life.

But the demands of new technology nodes are beginning to reach beyond the level of circuit design, influencing design choices at the chip, and even the system level. For example, consider high-speed serial interfaces. Today, Altera is shipping Stratix V FPGAs with highly-configurable 28Gbit/s transceivers, thanks to a combination of process, device and circuit innovations. But in today's systems-directed world, the industry's fastest integrated transceivers themselves are just the beginning of the story. Serial links require controllers fast enough to keep up with the transceivers. The controllers require on-chip busses fast enough, and buffers large and fast enough, to support them. And all of these blocks must meet energy-consumption requirements that depend on the particular system, its application, and its use models.

Accordingly, Altera's transceiver technology must offer choices. Some of these choices are at the circuit leveldifferent versions of the transceivers have been designed to operate at different speeds and with different levels of energy consumption. By selecting a chip from the tailored 28nm family, a system design team can match transceiver speed and energy-consumption to their specific system requirements.

Other decisions are at the block level. Should performance-critical and energy-hungry controllers such as PCI Express Gen3 or DDR3 be implemented in programmable cells, or in fixed hardware? Should such blocks connect into the programmable fabric, or to a hard-wired system bus, or both? The answers depend on the application.

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