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Identify drain-current conditions when computing power of multicore SoCs

Posted: 17 Jan 2012 ?? ?Print Version ?Bookmark and Share

Keywords:power numbers? multicore? drain current?

The automotive electronics targeted for safety applications are increasingly employing multiCPU architectures with on-chip redundancy to safeguard applications using minimal software overhead. On one hand, having on-chip redundancy is good for safety measures, but on the other hand it has attached baggage like higher die-area, higher noise, higher power consumption, etc.

This article discusses the factors that should be considered when calculating the power numbers of such SoCs. These factors if not decided judiciously may lead to inaccurate power numbers in the product datasheet, which could result in lost sales or customer dissatisfaction.

Power consumption of a device under typical run conditions is one of the important parameters specified on a datasheet. In the case of SoCs, the power consumption number depends on multiple factors like frequency of operation, modules enabled during the operation, CPU and DMA (direct memory access) operations with cache enabled/disabled, etc. For multiCPU (multicore) SoCs, another factor is whether the CPUs are working in lock-step or a decoupled parallel mode.

This feature discusses the various factors considered to define the typical Run-Idd (drain current) conditions (TRC) for the power measurement. This is a very important step before proceeding to make measurements and justify the power numbers on the datasheet. The analysis presented here is for a dual-CPU SoC, but is well applicable to all multiCPU SoCs.

Figure 1: Dual-CPU SoC.

Dual-CPU architecture
Figure 1 shows the architecture of a typical dual-CPU SoC. The blocks in blue implement on-chip redundancy which we call Sphere of Replication (SoR). Each SoR contains identical CPUs (e200z4), eDMA controllers, interrupt controllers, crossbar bus systems, system timers, software watchdog timers, etc.

The blocks in pink are redundancy checkers (RC), which check the outputs from both the SoR and signals fault to FCCU (fault control and collection unit) in case of a mismatch. The blocks in yellow are the modules accessible by both of the CPUs.

Dual-CPU SoCs may broadly operate in two modes:

Lock Step Mode (LSM): CPUs in both the SoRs execute the same instruction cycle by cycle and any differences between the outputs of the CPUs indicates a fault and triggers a reaction to prevent propagation of the fault and to put the microcontroller into a fail-safe mode.

Decoupled Parallel Mode (DPM): In this mode, each CPU runs independently. This mode of operation puts the chip into a symmetric multiCPU processor mode with both processors having individual control of their peripherals. DPM increased performance can be estimated as about 1.6 times the performance of the LSM operation at the same frequency.

Typical run conditions for current consumption
As discussed earlier, defining typical Run-Idd conditions (TRC) is the first and foremost step before proceeding to measure the power requirements of a SoC. Bear in mind that customers are interested in knowing the worst-case power requirements of the device, but still realistic enough to match closely with the most probable operation of their application.

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