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Signal chain basics: Clock jitter unveiled (Part 1)

Posted: 24 Jan 2012 ?? ?Print Version ?Bookmark and Share

Keywords:jitter? phase noise? ADCs? DACs?

In this article, we tackle the relationship between jitter and phase noise. This lays the foundation for future discussions on clocking data converters.

Time domain, frequency domain
Figure 1 depicts the nature of the information provided by measuring a signal in the time domain vs. the frequency domain. Both provide insight into the content of the signal and possible approaches to optimise the signal-to-noise ratio (SNR). It is important to understand where in the frequency spectrum the noise content of a signal resides because a system is susceptible to performance degradation due to noise within a specific bandwidth. Frequency domain measurements provide this insight.

Figure 1: Time domain vs. frequency domain measurements.

What is phase noise?
Phase noise is a frequency domain measurement that is the power spectral density of a signal's phase. To better understand the definition of phase noise, let's consider how it is measured. Figure 2 shows a typical phase noise measurement setup in which a clock oscillator is connected to a spectrum analyser.

Figure 2: Phase noise measurement.

A phase noise measurement has the following characteristics:

???The spectrum is considered symmetrical about the frequency (fC), therefore, only half (one side) of the spectrum is evaluated. This is called 'single-sided' phase noise.
???It is measured within a 1Hz bandwidth. It is assumed that the power level is constant within this bandwidth. Therefore, phase noise is a power spectral density.
???It is measured relative to the signal's power at frequency fC and is expressed in dBc/Hz.
???It is measured at various frequency offsets relative to the clock frequency. Sometimes datasheets record values at a few offsets, while others provide a phase noise plot as shown in figure 2.

Phase noise and jitter
Figure 3 shows the formulas needed to convert phase noise to RMS jitter. RMS Phase Error is determined by calculating the area under the single-side band phase noise plot L(f); integrated betwewen two frequency limits of f1 and f2. These limits are not arbitrary as many of the integration limits are determined by the characteristics of the system being designed.

Figure 3: Phase noise to jitter calculation.

Once RMS phase error is determined, the value is scaled according to the second equation in figure 3. It is important to note than whenever an RMS jitter value is referenced, the carrier frequency, the value in dBc/Hz, and the noise integration bandwidth all must be specified for the parameter to be meaningful.

By understanding random jitter and phase noise, you will be better prepared to explore how clock jitter impacts the performance of analogue-to-digital (ADCs) and digital-to-analogue converters (DACs), which we will cover at a future date.

Meanwhile, please join us next time when we will discuss RS232-to-RS485 converters used for industrial long-haul communication.

About the author
John Johnson is the Manager of Market Development and Systems Engineering for the Clocks and Timing Group of Texas Instruments. John has 30 years of experience in the electronics industry and has worked in the fields of product development, marketing, systems engineering, and business management. He holds a MSEE from Purdue University.

To download the PDF version of this article, click here.





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