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Startup tries many-core revolution

Posted: 26 Jan 2012 ?? ?Print Version ?Bookmark and Share

Keywords:many-core processor? CMOS? parallelization?

Startup Kalray SA is on a mission to launch a relatively general-purpose many-core processor. Kalray is claiming it can combine the hardware with necessary software to break through the many-core barrier with a 256 processor array integrated on a 28nm CMOS chip.

The company has its headquarters in Orsay near Paris, while its engineering base is in Grenoble, France. Kalray is led by Joel Monnier, a former vice president for central R&D at STMicroelectroncs. The company was founded in July 2008 and has raised more than $20 million in venture capital.

Kalray's chip was due in the fourth quarter of 2011, according to the company's website. It is not clear if that was achieved and the company has not responded a recent email request for information.

The company has dubbed its approach as Multi-Purpose Processor Array (MPPA) and claims that its architecture allows 256 processors, organized as 16 clusters of 16, to work in parallel and communicate via a network-on-chip just as clusters of computers do on the Internet. Kalray has chosen a proprietary very long instruction word (VLIW) architecture integrating a 32bit/64bit floating point calculation unit.

The chip is expected to deliver about 200GOPS at 400MHz clock frequency and a maximum performance of about 500GOPS at power consumption of about 5W.

However, such specifications cannot be easy to achieve. Kalray not only has to build a many-core processor in a leading-edge process but also demonstrate ways to make writing software transparent and easy and getting the code to run efficiently.

It is generally acknowledged that building many-core processors for well-chosen applications, such as PicoChip's array for base station protocol execution and NetLogic chips for networking is a tractable problem. However, making such an array that meets more general needs and which can power up and power down cores to deliver efficient processing for different types of application is notoriously difficult.

Plurality Ltd announced its HyperCore acceleration processor IP in April 2010. This was also a 256-core processor albeit one aimed at wireless infrastructure applications.

According to its website, Kalray is aiming its chip at a broader set of applications that can benefit from parallelization, imaging, telecommunications infrastructure, data security, network appliances and embedded applications.

Three years and $27 million
The company raised $19.1 million in 2008 and 2009. The company announced it had raised a Series B of $7.8 million in 2011. The company has 50 engineers and is backed by several French investment funds including: ACE Management, Inocap, Eurekap, CEA Investissement, Rh?ne Alpes Creation, Promelys, local funds and other private investors as well as by the French government agency OSEO, which provides support to startups.

Along with the chip, Kalray is offering development boards and the AccessCore software development environment, the website said.

AccessCore supports a C-based programming model but support also varies between different user profiles from Linux support for legacy functions up to a dataflow environment that can maximize use of the array. Standard GCC & GDB technologies are used for compilation and debug.

"Kalray's technology has been developed with many OEM partners across several vertical markets, as well as partnering with third-party software vendors," said Monnier, in a statement issued May 2011. "Our first processor achieves a global processing power of 500 billion operations per second, along with a much lower power consumption than competitive solutions. Embedded designers will get the benefit of high processing power, low power consumption and high level programming to develop innovative applications in the fields of image processing, signal processing, control, communications and data security. The access cost of MPPA processors makes them optimum for all low to medium volume applications."

The 256-processor chip allows array extension by the clustering of several chips and the I/O offering includes generations 2 and 3 of PCI Express, Ethernet able to run at up to 40-Gbits per second and general purpose I/Os. Memory controllers for flash and DDR DRAM allow for external storage of up to 128GB. And is described as being in a standard 40 x 40mm BGA package.

And, as one might expect, the 256-processor chip is the first in a projected family. The MPPA family scales from 16 to 64 clusters per chip. The 1024-core version delivers up to 2Tops (tera operations per second). The MPPA also includes 4 to 8 Interlaken interfaces for multiMPPA chip systems and connection to FPGAs.

- Peter Clarke
??EE Times

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