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Samsung, Cadence partner in nanometer SoC design

Posted: 10 Feb 2012 ?? ?Print Version ?Bookmark and Share

Keywords:design-for-manufacture? node design? SoC?

Samsung Electronics Co. Ltd's Samsung Foundry has teamed up with Cadence Design Systems Inc. to develop a design-for-manufacturing (DFM) infrastructure. According to them, the partnership will address physical signoff and electrical variability optimization for 32, 28 and 20nm SoC designs.

The technology tackles both random and systematic yield issues, providing customers with a proven foundry option for advanced-node designs built on the Cadence Encounter digital and Cadence Virtuoso custom/analog implementation solutions.

The Cadence in-design approach to Silicon Realization moves traditional DFM steps into the implementation stage of digital and custom chip design, the company stated. The approach is aimed at boosting productivity, predictability and profitability while reducing risk. The DFM flows developed includes Cadence Pattern Classification and Search, Cadence CMP Predictor, Cadence Litho Physical Analyzer and Cadence Yield Analyzer and Optimizer.

nanometer SoC

The DFM collaboration targets 32, 28 and 20nm ICs.

"As we expand our customer base at advanced process nodes, customers require various design flows," noted Kyu-Myung Choi, SVP of infrastructure design center, Samsung, "By teaming with Cadence to build a strong foundry ecosystem for advanced node designs, we've achieved numerous benefits we can pass along to our customers such as reducing risk and speeding time to market. We've enjoyed great success at 32 and 28nm with Cadence, and we have now extended our advanced DFM flow to 20nm as well."

Manufacturing complexity is growing exponentially at advanced nodes, and it impacts design cycle time and time to yield compared to previous nodes. With the new infrastructure optimized for advanced nodes, Samsung Foundry is able to use the hierarchical design approach and pattern matching to perform effective and accurate systematic failure analysis. And the Cadence production-proven in-design DFM prevention and optimization in Cadence Encounter digital and Cadence Virtuoso custom/analog implementation solutions enables first-time-correct silicon.

The Cadence pattern classification technology allows Samsung Foundry to classify the yield detractor patterns into easily usable pattern libraries. The infrastructure enables Samsung Foundry's customers to leverage the in-design and signoff pattern matching with automated fixing flows in Encounter and Virtuoso. Another innovation from this collaboration is the development of a chip-based CMP analysis flow to enable early convergence of topography yield issues in advanced digital and custom designs, stated the company.

- Paul Buckley
??EE Times

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