Challenges, opportunities of the 2.5D/3D ecosystem

For decades, Moore's law has predictably driven Silicon scaling, and, semiconductor manufacturing has been based largely on planar (2D) technology. The 2D design and manufacturing sequence has had its clearly defined phases: specification, design, fabrication, assembly and test. Each phase is a well-defined function with understood borders between each other. As the semiconductor manufacturing world moves into the "More than Moore" 2.5D/3D space, a wealth of opportunities are becoming available that further increase the functionality and performance of semiconductor ICs. For example, silicon designers increasingly find that by designing a Silicon system in 2.5D/3D, they are not limited to using a single Silicon technology node (e.g., 40nm or 28nm CMOS) or a single technology (e.g Logic, DRAM, Flash). Enabled by 2.5D and 3D Silicon manufacturing, designers can now design and build high-performance and energy-efficient systems using heterogeneous technologies such as CMOS (including multiple logic, memory technology nodes), MEMS, Si Photonics, etc.

While opportunities abound, moving to 2.5D/3D manufacturing has posed significant challenges to designing, fabricating, assembling and testing of 2.5D/3D ICs. Integrating heterogeneous technologies call for the industry and R&D organizations to address these challenges. All these challenges call for a steep learning curve across existing borders, design-houses, fabs, assembly, test providers, and re-adjustment of roles and responsibilities in the manufacturing flow. As such, a collaborative approach is needed to ensure the industry meets the goals in a timely manner. Industry-sponsored-consortia play a crucial role in collaborative exploration by driving research-and-development in a cost-effective manner with the goal of building strong manufacturing eco-systems that are 2.5D/3D aware.

Figure 1 shows an advanced 2.5D demonstration vehicle that the Institute of Microelectronics (IME) is designing for fabrication at our 300mm advanced interconnect and packaging facility in Singapore. The vehicle is essentially a future data-communication system that combines three heterogeneous elements on our Through-Silicon-Interposer (TSI) platform: (a) Optical-Sub-Assembly (OSA), (b) an FPGA that can function as a network processor and (c) high-speed 3D Wide-IO memory. The three elements are indeed manufactured in heterogeneous technologies: the optical sub-assembly manufacturing is based on a CMOS-compatible Si-photonics technology using SOI wafers. The FPGA is manufactured in an industry-leading 28nm foundry CMOS process. The 3D memory uses Tezzaron Semiconductor's FaStack? technology to produce low-latency, low-power, high-speed memory that is essential for future Tb/sec data communication systems. The FPGA can be programmed in a network-processor/switch configuration that communicates with the OSA and uses the closely assembled memory to store, switch/transmit data-packets. Having optical communication with low-latency memory right next to the network-processor/switch is seen by industry as a critical part of achieving sub-pJ/bit energy consumption in server-farms.

As another example, Figure 2 shows a 3D system that integrates vertically MEMS sensor/energy-scavenger, embedded passives, digital + memory and RF/analog functions. An miniaturized antenna on the top layer transmits data in and out of this 3D system. Such a miniaturized system consists of separately manufactured thin layers of Silicon from heterogeneous technologies. The layers of Silicon communicate with one-another through TSVs. Such 3D systems can be used in many applications including medical devices where the device can collect data inside the human-body and transmit it via the antenna wirelessly.

From the aforementioned two examples, some of the key technical challenges with designing 2.5D and 3D systems needed to be addressed are: lack of 2.5D/3D process design kits (PDK) with standardized design-flow, power-integrity, thermal management, concern of electromagnetic interference, signal-distribution, electrical/mechanical reliability issues. In designing 2.5D/3D ICs, one needs to have an accurate PDK for the Silicon-interposer and TSV as part of a standardized design flow. Figure 3 shows the key elements of the Silicon-proven process design kit that IME is offering to the design community to reduce design cycle-time and improve design-accuracy.