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GbE controller, IP cores boost Ethernet SoC deployment

Posted: 23 Feb 2012 ?? ?Print Version ?Bookmark and Share

Keywords:40/100 Gigabit Ethernet? IP core? media access controller?

Cadence Design Systems Inc. has unveiled its 40/100 Gigabit Ethernet (GbE) media access controller (MAC) and physical coding sub-layer (PCS) IP cores that the company said speed up deployment of SoCs for networking and high-performance computing. The devices support the latest version of the IEEE 802.3ba-2010 Ethernet specification and sub-specifications including Energy Efficient Ethernet, added Cadence.

With more than 50 tapeouts of Ethernet designs from 1GbE up to 40GbE, Cadence offers both the design IP and integration support required to ensure silicon success. Cadence's Ethernet solutions include unique capabilities in verification IP (VIP), emulation, virtual prototyping and silicon-package-board co-design, the company noted.

The IP includes a host of configurable features such as Ethernet address match logic and frame and priority-based flow control mechanisms for application-based customization of traffic control. In addition, a programmable inter-frame gap feature enables precise packet flow control to avoid equipment overload.

Additionally, the IP provides comprehensive monitoring features such as error/status word for each frame that is transmitted and received, remote monitoring (RMON) and management information base (MIB) support. The 40/100 GbE MAC IP supports Gigabit media independent interfaces (XLGMII and CGMII) for connection to the attached PHY layer device, whereas the 40/100 GbE PCS IP supports integration with four/ten 10 Gigabit SerDes.

The design IP, including MAC and PCS, as well VIP, emulation and virtual prototyping support, are available.





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