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Designing high frequency synchronizer with programmable MTBF features

Posted: 29 Feb 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Synchronizer? data transfer? mean time between failures? metastability?

The different scenarios of flip-flops entering into metastable states and the maximum number of clk cycles required for valid synchronized output for different scenarios are shown in figure 3 in the form of a flow chart. Just like a standard two flip-flop synchronizer, the proposed synchronizer can be defined as a synthesizable IP that can be readily used in an SoC environment.

Simulation results
The proposed synchronizer has been designed in CMOS90 technology with clk frequency equal to 2GHz. Figure 4 shows the generation of divided by 4 clock, clk_gated. The other simulated waveforms are also shown, which correspond to the circuit nodes shown in figure 2. It is clear from figure 4 that the periods of clk and clk_gated are 500ps and 2ns respectively.

Figure 4: Simulation waveforms showing generation of clk_gated clock.

For a case in which the data does not fall in the setup-hold window of the clk, the output of FF1 will not be in a metastable state and the synchronized output will occur between 5 and 8 clk cycles. When the data falls in the setup-hold window of the clk, the output of FF1 becomes metastable. This situation gives rise to two sub-cases:
(i) first edge of the clk_gated coincides with second clk edge.
(ii) first edge of the clk_gated coincides with 3rd, 4th or 5th clk edge.

In sub-case 1, FF2 captures the metastable data at second clk edge. However, the time available to FF2 to resolve its metastable state has been increased to four times (= 4/fclk). If after the four clk cycles, data_mid2 settles to its correct logical value, FF3 will capture the correct data at 6th edge of clk. On the other hand, if after the four clk cycles, data_mid2 resolves its metastable state in an undesired logical value, FF3 will capture the correct data at 10th edge of clk. For sub-case 2, the output of FF1 comes out of metastable state at the second clk edge before it is captured by FF2. FF2 captures the correct data at 3rd, 4th or 5th clk edge and FF3 captures the correct data at 7rd, 8th or 9th clk edge respectively.

Figure 5 shows the simulation result of clk_out generation. This is an example of clock gating scenario where clk_out starts coming in response to a low-to-high transition in data. There is no glitch in the first cycle of clk_out because of a synchronized start. This result shows a data signal synchronized with a 2GHz clock.

Figure 5: Simulation waveforms showing generation of clk_out clock.

Conclusion
In this fully parameterized, gigahertz-range synchronizer circuit designed to provide NeN times increase in MTBF value as compared to a standard two flip-flop synchronizer, the division factor N is user programmable and provides a tradeoff between synchronized output latency and MTBF value. A larger value of N provides higher MTBF but at the cost of additional latency. As compared to a standard two flip-flop synchronizer, the proposed synchronizer introduces an extra NAND gate delay in the synchronized output which is very much reduced in today's deep sub-micron CMOS technologies. Simulation results in CMOS90 technology with 2GHz input clock frequency show the expected behavior of the proposed synchronizer.

References
[1] Ran Ginosar, "Fourteen Ways to Fool Your Synchronizer," Proceedings of the Ninth International Symposium on Asynchronous Circuits and Systems (ASYNC03), pp. 89-96.
[2] Chuck Brown and Kamilo Feher, "Measuring Metastability and its Effect on Communication Signal Processing Systems," IEEE Transactions on Instrumentation and Measurement, vol. 46, pp. 61 C 64, Feb. 1997.

About the author
Sanjay Kumar Wadhwa received his B. Tech. degree in Electronics and Communication Engineering from National Institute of Technology (NIT), Kurukshetra, India in 1996. Since then, he has worked in the field of analog and mixed signal designs for various applications. He is presently working with Freescale Semiconductor India design center in the field of PLLs and low power analog circuits. He has published 14 papers in various VLSI conferences, has 4 defensive publications and holds 16 US patents. He has been recognized as a Distinguished Innovator by Freescale Semiconductor.

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