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Designing high frequency synchronizer with programmable MTBF features

Posted: 29 Feb 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Synchronizer? data transfer? mean time between failures? metastability?

Synchronizer circuits are typically employed in modern System on Chip (SoC) designs to facilitate the reliable data transfer between independent clock domains [1, 2]. As design geometry shrinks and clock speeds approach the gigahertz range, the design of synchronizer circuits becomes a challenging task. Metastability (the ability of a digital electronic system to persist for an unbounded time in an unstable equilibrium or metastable state) is a key factor to be considered. The mean time between failures (MTBF) value, which is a figure of merit related to metastability, degrades sharply when input clock and/or data frequency is increased, as per the synchronizer MTBF formula given in this equation:

In the equation, Fclk and Fdata are input clock and data frequency respectively, tMETA is the time delay allowed for metastability to resolve itself, C1 is a constant representing the metastability catching setup time window and C2 is a constant describing the speed with which the metastable condition is resolved.

The possible ways to increase MTBF are by cascading more flip-flops in the synchronizer circuit or by running the synchronizer at a slower frequency. In both the cases, tMETA value increases and the MTBF value increases exponentially as per equation (1). The proposed synchronizer enhances the MTBF value by dividing the high frequency input clock by a user defined division ratio, N.

With a standard two flip-flop synchronizer, the delay introduced between the input and the synchronized output is equal to one flip-flop's clock-to-output delay (Tcq) plus the delay of an AND gate (Tand). To increase the MTBF, if a standard two flip-flop synchronizer is run with a divided clock, the total delay between the input and the synchronized output will become 2*Tcq + Tand. The additional Tcq delay is contributed by the clock divider circuit. Due to this extra Tcq delay of a flip-flop, a glitch may appear in the synchronized output if the total delay is more than the OFF period of the input clock.

The situation will further degrade if the input clock duty cycle is more than 50%, further reducing the OFF period of the input clock. In the proposed synchronizer, instead of an extra Tcq delay contributed by the clock divider circuit, only a NAND gate delay (Tnand) is added, which is much less as compared to Tcq. The typical values of Tcq and Tnand are approximately 300ps and 30ps respectively in 90nm CMOS technology. Thus, the total delay becomes Tcq + Tand + Tnand and the proposed synchronizer is able to run at a much higher frequency as compared to a standard two flip-flop synchronizer.

Figure 1: Block diagram of the proposed synchronizer.

The circuit
Figure 1 shows the block diagram of the proposed synchronizer. The asynchronous input data is captured by the input flip-flop (FF). The output of the input FF is captured by a standard two flip-flop synchronizer, running on a divided input clock.

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