Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Amplifiers/Converters

Designing high frequency synchronizer with programmable MTBF features

Posted: 29 Feb 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Synchronizer? data transfer? mean time between failures? metastability?

Figure 2 shows the circuit diagram of the proposed synchronizer. The input clock, clk, goes to a divide by 4 circuit (N=2) composed of flip-flops FF4 and FF5. This divider can be made programmable to divide by N=2, 3, 4 etc. The flip-flops FF2 and FF3 form a standard two flip-flop synchronizer which is driven by the rising edges of the generated clock, clk_gated. The frequency of clk_gated is equal to one-fourth of the frequency of clk.

As shown in figure 2, the delay between clk and clk_gated is equal to the delay of a NAND gate, NAND1. The overall MTBF of the synchronizer will be the MTBF of FF1 (MTBF1) times the MTBF of the synchronizer composed of FF2 and FF3 (MTBF2).

Figure 2: Circuit diagram of the proposed synchronizer.

Because clk and data are asynchronous, FF1 can enter into a metastable state whenever a transition at its data inputwith respect to a transition at its clock inputhappens in the setup-hold window, which is typically 100ps-150ps. Similarly, FF2 can enter into a metastable state whenever a transition at data_mid1 with respect to a transition at clk_gated happens in the setup-hold window.

It is clear from figure 2 that even if FF2 output, data_mid2, becomes metastable, the time it will get to resolve the metastable state will be four times the time period of clk. Also, since the frequency of clk_gated is one-fourth of clk, the overall MTBF improvement will be 4e4 (~218.4) times as compared to a standard two flip-flop synchronizer. Qualitatively, because of quadruple increase in tMETA, probability of FF3 going into metastable state decreases significantly. In general, dividing the input clock by N improves the overall MTBF by NeN. However, an increase in N also increases the number of clk cycles required before the synchronized output, data_sync, appears. The number of clk cycles required depends upon relative timing of data transition at data and data_mid1 with respect to clk and clk_gated respectively, and whether FF1 and/or FF2 entered into a metastable state.

Figure 3: Flow chart for the proposed synchronizer.

For applications where this additional latency is immaterial, MTBF can be increased at the expanse of latency, with only marginal increase in the delay between the clk and the synchronized output. Typically, MTBF is designed to be at least ten times the expected lifetime of the product.

?First Page?Previous Page 1???2???3?Next Page?Last Page

Article Comments - Designing high frequency synchronize...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top