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Signal chain basics: Boss, master and slave in audio clocks

Posted: 02 Mar 2012 ?? ?Print Version ?Bookmark and Share

Keywords:I2S? master clock? DAC? ADC?

When audio topics are discussed, there is a chance that I2S would be mentioned. It's a synchronous method of transferring stereo audio data from one point to another.

Most engineers believe that I2S has three different signals:
1. Data: as an input, or an output
2. Bitclock (BCK): the signal that establishes the boundary between adjacent bits in the data streams
3. Left/Right Clock (LRCK)/Wordclock: A slower clock, running at the sample rate, with a 50 percent duty cycle, which establishes the boundary between adjacent channels (left and right) in the data stream.

The unsung hero of I2S, and mostly ignored by digital signal processors (DSP) programmers and other processor junkies, is the master clock (MCK), which may also be called the system clock (SCK). The master clock (MCK/SCK), typically is a clock that is 64, 128, 256, 512 times the sample rate (FS). It can be provided directly through an input pin or it can be generated internally in some devices by a phase-locked loop (PLL).

Typically, DSPs don't require an audio master clock, as they can be processing data at a completely different rate, and dropping data into output buffers (or receiving data through input buffers) at a rate driven by the BCK and LRCK.

Once you step outside of your processor, the audio master clock becomes much more critical. Most audio converters with MCK/SCK inputs require the clocks to be synchronized, while some are allowed to be out-of-phase. This means that they really need to be sourced from the same high-speed clock, and simply divided down. Some customers I've talked with have the brainwave, "Hey, my ADC needs an MCK, but it's far away from my DAC. Therefore, I'll use local crystal next to each converter...." An understandable idea, but please: DON'T DO IT!

When you buy a crystal, you aren't guaranteed that it's exactly 48.000kHz. Your analog-to-digital converter (ADC) crystal could be running at +5 percent accuracy and the digital-to-analog converter (DAC) could be running at C5 percent accuracy. This could spell disaster for your design! Read on to understand why.

Figure 1: Generic ADC block diagram. (Click on image to enlarge)

Master clock in audio ADCs
As shown in figure 1, a high-speed master clock (e.g., 24.576MHz clock) is used to drive the oversampling modulator in an ADC. The data from the oversampling modulator is then decimated down into the sample rate given by the LRCK.

When an ADC is running in master mode (generating the BCK and LRCK as outputs), then the ADC simply divides the MCK/SCK to generate the LRCK and BCK signals. Voila! The LRCK/BCK and master clock are synchronized C and probably in phase (unless it's an unusual divider).

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