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Imec, Renesas roll 250 MSPS ADC for WiFi, LTE-A

Posted: 27 Feb 2012 ?? ?Print Version ?Bookmark and Share

Keywords:SAR ADC? WiFi? LTE advanced?

Imec and Renesas Electronics Corp. have presented a successive-approximation register (SAR) ADC aimed at wireless receivers for next-generation high-bandwidth standards such as LTE-advanced and WiFi (IEEE802.11ac). Unveiled at the recent International Solid-State Circuit Conference (ISSCC2012), the device boasts enhancements in power efficiency and speed.

According to the organizations, the SAR ADC architecture is an answer to the need for much faster low-power ADCs with small form factor. The ADC is a 1.7mW, high resolution, two-step interleaved pipelined SAR ADC achieving a record power efficiency of 10fJoule per conversion step at a sampling speed as high as 250MSPS.


1.7mW, high-resolution (11bit) pipelined SAR ADC with 250MSPS sampling speed

This result is obtained with a new converter architecture based on prior groundbreaking ADC designs from Imec, exploiting the opportunities of modern advanced CMOS technologies. The design uses completely dynamic circuits, such that the power consumption scales linearly with the sampling frequency, and is implemented with a maximum amount of digital content, leaving the comparator as the only analog building block.

The ADC prototype has been manufactured in 40nm CMOS with a core chip area of 0.066mm2. Measurements show a DNL and INL of respectively, 0.8/-0.5 and 1.1/-1.5 LSB. The dynamic performance is characterized by 62dB SNDR (10.0 ENOB) at 10MSPS, which is maintained up to 9.5 ENOB level for a sampling speed of up to 250MSPS. The power consumption is 6.9pJoule per conversion (70?W at 10MSPS, 1.7mW at 250MSPS), resulting in energy efficiency of 7-10fJoule per conversion-step.

Also at ISSCC, Imec and Renesas presented a new way to connect the ADC architecture with the complete radio architecture. To improve the power efficiency of the total receiver system, and avoid issues related to large input capacitors in a voltage-domain ADC system, a 3.2-51.2mSiemens current domain variable-gain transconductor (VGA) was used to drive a charge-domain SAR ADC with no overhead, and as such minimize the overall system power consumption. A 10b 10-80MSPS VGA-ADC prototype in 40nm CMOS achieves 70dB DR while consuming less than 5.45mA from a 1.1V supply.

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