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Introduction to 2.5D

Posted: 07 Mar 2012 ?? ?Print Version ?Bookmark and Share

Keywords:2.5D? 3D? 65nm?

The IC industry is intensifying efforts to make 2.5D and eventually 3D IC technology a mainstream reality.

The vision of a 3D IC is promising, but some industry watchers believe the 2.5D market to be more than a steppingstone to true 3D design. They say 2.5D technology has staying power. Leveraging it industry-wide will require evolutionary, rather than revolutionary, adjustments to current design flows and the supply chain.

In its Virtex-7 2000T, Xilinx Inc. places several dice side by side on a passive silicon interposer. The 2.5D technology has marked advantages in capacity, performance, form factor and system power consumption over traditional multichip implementations.

The 2.5D method is similar to implementing discrete ICs on a pc board, but on a much smaller scale and with a substantially higher interconnection bandwidth. With 2.5D technology, companies can create devices that exceed the capacity increases predicted by Moore's Law. It also is possible to mix and match dice to create what are essentially complete systems on one interposer.

The industry envisions that 3D ICs will let companies stack two or more dice (active-on-active) and achieve new levels of system integration by stacking the chips usually mounted on a pc board in one or just a few devices.

In many ways, 2.5D is less complex than 3D. For example, thermal management could require new thermally conductive materials for active-on-active 3D implementation. In 3D ICs, through-silicon vias (TSVs) in active silicon will affect the neighboring transistors and will create uneven distribution of device characteristics. Testing of 3D ICs will require new test methodologies and test hardware.

Cost is another factor that favors 2.5D. Xilinx leveraged existing technologies to keep down the cost of stacked-silicon-interconnect (SSI) technology.

For example, Xilinx implemented the interposer in 65nm silicon, which is less expensive than most new materials or 28-nm silicon.

About the author
Ivo Bolsens is senior vice president and chief technology officer, with responsibility for advanced technology development, for Xilinx Research Labs and the Xilinx University Program (XUP). Bolsens joined Xilinx in June 2001 from the Interuniversity Microelectronics Center (IMEC; Leuven, Belgium), where he was vice president of information and communication systems. Bolsens holds a PhD in applied science and an MSEE from the Catholic University of Leuven.

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