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Solve hierarchical signal planning, routing issues

Posted: 08 Mar 2012 ?? ?Print Version ?Bookmark and Share

Keywords:analog/mixed-signal? digital IC? Floor planning? routing?

Market requirements are pushing custom and analog/mixed-signal (AMS) IC providers to develop ICs with ever-increasing complexity and performance. Current custom ICs are outgrowing the capabilities of conventional custom design techniques that involve traditional point tools, schematics, SPICE-level netlists, manual layout tools, manual routing, plus some scripting to improve design throughput. Design limitations are especially pronounced in the areas of hierarchical floor planning, signal and bus planning and routing, design change incorporation, and project coordination.

What about using advanced digital IC design tools to help automate the custom design effort? Advanced digital IC floor planning, signal planning, and routing tools rely on the highly standardized digital design ecosystem, and remain largely ineffective when faced with custom IC design challenges that include: irregular libraries, limited model availability, limited metal stacks, unusual physical topologies, extremely deep design hierarchies, lack of routing grids, lack of placement grids etc. Some of the approaches that have been used in digital design automation can be adapted to support custom IC signal planning and routing. However, don't expect solutions from large digital IC design tool providers, the custom market space remains too small and too fragmented to justify the effort. Future solutions will largely come from smaller specialized custom design automation suppliers.

This article gives an overview of a proven methodology that relies on hierarchical custom design tools that can be used to resolve hierarchical signal planning and routing issues. The following topics will be covered: floor planning, power planning, bus long net and datapath planning, signal planning and routing, route fixing and optimization, and guided design flows.

Floor planning
The main starting point for optimizing hierarchical signal planning and routing involves hierarchical floor plan optimization. Floor planning for custom designs requires a great deal of flexibility, so support for both top down and bottom up approaches is needed to help optimize routing paths, soft macro (block) floor plans and soft macro (block) pin placements.

From a top down perspective, top-level pins that have fixed positions, such as I/O-related signal pins, should be visible to the rest of the design in order to help optimize associated routing and soft macro pin positions. From a bottom up perspective, designs often contain hard macros or intellectual properties (IPs) with fixed pin positions that should be placed in specific optimal locations. These bottom up, hard macro locations and pin positions should be used to help optimize soft macro pin positions and related signal routing. Floor planning is an iterative process, involving many possibilities and permutations, and using an automated tool that supports rapid hierarchical floor plan generation for custom designs will hasten the process. Early floor planning steps usually involve fixing hard macro positions based on I/O pins and dataflow, since these will impact more flexible parts of the design. The next steps involve sizing soft macros and performing trial and error block and pin placement to refine the floor plan.

Power planning
After determining the basic floor plan and block sizes, the initial power plan should be added to the design. Aside from hard macros that contain internal power and ground routing, the power plan is normally added in a top down manner. The power and ground mesh should always be added before signal and bus routing, otherwise resources needed for power routing may be blocked by the signal routing. For custom designs with extremely limited metal layers, where the power routing is on the same layer as the signal routing, the power routing should be added before defining the block-level pin locations, otherwise power pin positions may be blocked by signal pins.

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