Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Solve hierarchical signal planning, routing issues

Posted: 08 Mar 2012 ?? ?Print Version ?Bookmark and Share

Keywords:analog/mixed-signal? digital IC? Floor planning? routing?

Power planning parameters can be easily defined using a GUI-based power planning tool that supports working at a high level of abstraction by creating power guides for all power domains. These power guides can include attributes such as (absolute/relative) location and shape, power supply names, routing layers, routing widths, via topologies, etc. Once defined, the power nets can then be pushed down into the soft macros for use by their design teams. When the design is reassembled, the soft macros are brought back into the top level and connected to corresponding top-level supply routes.

Datapath planning
The next major step involves adding top-level buses. This is best achieved using a bus planning tool (e.g., the Pulsic Unity Bus Planner) that allows users to quickly input top-level GUI-based bus guides, which provide information used to define and optimize the top-level routing paths of corresponding buses. Signal routing for each guided bus follows the same topology, and uses the same layer and vias. Those buses that don't require routing guides can be routed as ordinary signals.

Inputs for bus guidance include: physical topology, signal ordering, optional shielding, optional signal interleaving with other buses, metal layer selection, via selection, and via topology selection for forward or backward via sets, etc. Various generic controls can be provided by an attribute editor that can define buses by combining signals together; set signal routing widths and set signal route spacing; select X, Y routing layers; etc. Bus bits also can be reordered to help minimize cross-talk effects.

Once the bus guides are in place, the buses can be routed. Afterwards, the topology-based repeater planner (a bus planner tool feature) can specify locations for bus repeater insertions needed to speed up signal propagation and minimize cross-talk effects. The next step involves automatically placing and connecting the repeaters to the existing bus routing. By design, propagation delays for signals on the same bus will be very close since their routing and buffering remain similar.

Figure 1: Example of bus routing guides for two buses. Notice that the horizontal bus guides overlap. This indicates that the horizontal routes for the two buses are to be interleaved.

Figure 2: Bus signal routing for the two bus guides in figure 1. Via ordering can be selected to minimize metal crossings when buses change routing directions.

Signal planning and routing
Signal planning is a time-consuming process that often impacts design schedules and area requirements for hierarchical custom designs. This process would benefit from the use of a comprehensive signal planning tool such as the Pulsic Unity Signal Planner that supports two modes: strictly-biased routing and multiple-bias routing that employs a jumper layer. Strictly-biased mode limits signal routing to user specified X and Y routing layers without exceptions, and is a capability provided by many routing tools. The multiple-bias routing mode is an advanced capability that supports signal routing on the same metal layer for both X and Y directions. At the same time, a jumper layer can be defined and used to cross other signals that are blocked by potential X or Y multibiased routing. Processes with limited metal stacks that include a high resistance routing layer could use the high resistance layer as a jumper layer, thereby increasing available routing resources without seriously degrading timing.

?First Page?Previous Page 1???2???3?Next Page?Last Page



Article Comments - Solve hierarchical signal planning, ...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top