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Solve hierarchical signal planning, routing issues

Posted: 08 Mar 2012 ?? ?Print Version ?Bookmark and Share

Keywords:analog/mixed-signal? digital IC? Floor planning? routing?

Designers can employ biased routing capabilities to create various complex space-saving routing topologies, such as "L", "C", "J", "H", etc. Furthermore, signal routing can be stacked into elaborate patterns for processes with deeper metal stacks. Differing biased-signal planning attributes can be applied to different signals so that designers can customize routing in different parts of the design.

The following routing capabilities can be used to automate custom signal routing.

1. A shape-based router that supports Manhattan or angled routing and views the entire database at one time. It sorts and orders nets to minimize crossings and produce straight routes, unlike typical bin-based routers, which may detour signals through less congested routing bins.

2. A bus planner-router to support bus guidance, bus routing and repeater insertion.

3. A global router that provides rapid congestion analysis needed to optimize channel sizes.

4. A spine and stitch router for designs with long, thin aspect ratios and limited routing resources. A single spine route would be made in the resource-limited direction; perpendicular stitch routes plus vias are then used to connect the spine route to the loads.

Figure 3: An Example of a spine and stitch route. The horizontal spine route is in a resource-limited direction, while perpendicular stitch routes make the connections to the loads.

Route fixing and optimization
After the design is routed, some post-route optimization and error fixing is normally required. A smooth routing command removes unnecessary vias, jogs, corners, and segments while evening out the spacing between adjacent routes, which boosts production yields. The design database is automatically checked by an internal design rule checking (DRC) tool that ensures that the routing in the final routed database will pass DRC checks run at verification. Automated checking and fixing capabilities for antenna violations and layer density are also provided.

Guided design flows
Custom design projects have inherently diverse design tool requirements, forcing custom design automation tools to provide a wide variety of features and capabilities to meet the needs of widely differing custom design projects. Only a limited subset of these commands, options and settings would be applicable to any particular design project.

Guided design flows such as those in the Pulsic Unity Chip Planner are essential for making custom design automation software tools easier to use. Guided flows can provide the necessary step-by-step design automation commands needed to work on a targeted custom design while bypassing design tool features, capabilities, and/or flow steps that aren't needed. This simplifies custom design flows and reduces the learning curve.

To meet the demands of increasing complexity and performance for custom and AMS ICs, custom designers will benefit from a proven methodology and hierarchical custom design tools with the following signal planning and routing capabilities:

???A diverse set of hierarchical signal planning and routing features that support top down and bottom up approaches.
???A hierarchical design database supporting seamless block and pin placement plus optimization.
???Rapid hierarchical prototyping to explore "what-if" scenarios.
???Automated routing solutions including: spine and stitch, shape-based, multitopology, and multiple-biased routing.
???Post-route optimizations: via and jog minimization; automated checking and fixing for DRCs, metal density, and antenna violations.
???User-friendly guided design flows

About the author
Bob Eisenstadt, Senior Technologist, Pulsic, Inc. Prior to joining Pulsic, Bob was Principal Engineer at Rambus and at Alchip. He has held senior design roles at Qthink, Silicon Image, 3dfx, SGI, VLSI Technology and was co-founder of Silicon Mosaic where he developed and patented an early low power design solution. Bob holds a BSEE from Cornell University plus an MSEE and an MBA from Santa Clara University.

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