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Wide I/O driving 3-D with TSV

Posted: 09 Mar 2012 ?? ?Print Version ?Bookmark and Share

Keywords:through-silicon vias? I/O? RDIMMs?

The standard for Wide I/O mobile DRAM, released by Jedec in January, uses through-silicon vias (TSVs) to connect DRAM to logic on three-dimensional integrated circuits. With its 512bit data interface, JESD229 Wide I/O Single Data Rate (SDR) doubles the bandwidth of the Low-Power Double Data Rate 2 (LPDDR2) specification without increasing power consumption.

Devices that use through-silicon vias (TSV) connections between homogeneous dice are already available. Wide I/O is leading the way to TSV connections between heterogeneous dice.

Among the companies offering devices with homogeneous TSV connections are Xilinx, whose Virtex-7 2000T field-programmable gate arrays use logic connected to logic, and Samsung, whose 32-GB registered dual-in-line memory modules (RDIMMs) use DRAM stacked with DRAM. There are many good reasons for homogeneous TSV connections. Xilinx claims its devices offer a hundredfold improvement in die-to-die connectivity bandwidth per watt with one-fifth the latency; Samsung claims a 40 percent reduction in power.

Even a device that has twice as many cells on it than the dice we can produce today can use TSVs to connect two homogeneous dice. But what happens when a device has more types of different cells than the dice we can produce today?

The full potential of TSV technology comes with the ability to connect dice with different physical properties. Though it is possible to put logic, memory, radio-frequency (RF), analog, power, and image-sensing circuits all on the same piece of silicon, it may be preferable to put them on separate dice for the best performance at the lowest cost.

Figure 1: A 3D-IC using TSVs.

Like many new technologies, TSV has an initial cost that is higher than the technology it replaces, and simply reducing the cost of the dice in the stack may not be enough to justify its use. The ideal applications for TSV technology are those that can benefit from the dramatic improvement it brings to bandwidth, latency and power.

Consider the interface between the logic die and DRAM in a next-generation smartphone, tablet or subnotebook. These next-generation devices will require about 100 Gbit/second of peak bandwidth between logic and DRAM, which is the highest-bandwidth chip-to-chip interface typically found inside this class of product. Many logic Fmanufacturing processes include the ability to create some embedded DRAM. But it is substantially cheaper to produce large amounts of DRAM on a dedicated DRAM process.

Today's 2-Gbit DDR3 devices, each of which contain 2 billion transistors, can sell for less than a dollar per chip, easily meeting the economic test for making the logic die and the DRAM die on different processes. Because memory latency is a key metric in the performance of systems-on-chip (SoCs), a low-latency DRAM interface is desirable. In a smartphone, the DRAM under heavy load can consume 25 percent of all power used: any reduction in power per bit transferred can substantially improve battery life.

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