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A*STAR, Applied Materials unveil 3D chip packaging R&D center

Posted: 09 Mar 2012 ?? ?Print Version ?Bookmark and Share

Keywords:3D? chip packaging? manufacturing solutions? semiconductor R&D?

Manufacturing solutions provider for the semiconductor, flat panel display and solar photovoltaic industries, Applied Materials Inc. and the Institute of Microelectronics (IME), a research institute under the Agency for Science, Technology and Research (A*STAR), have officially opened the Center of Excellence in Advanced Packaging at Singapore's Science Park II.

The opening ceremony was presided by Singapore's Minister for Trade and Industry, Lim Hng Kiang.

The center was built through a combined investment of over $100 million from Applied Materials and IME. It boasts of world-class facilities featuring a 1,300m2 Class-10 cleanroom and is equipped with a fully-integrated line of 300mm manufacturing systems to support the research and development of 3D chip packaging, a critical growth area for the semiconductor industry.

"Today, we are not only opening the most advanced wafer level packaging lab of its kind in the world, but we are also opening a new product development capability for Applied Materials in Asia," said Mike Splinter, chairman and CEO of Applied Materials. "This center will strengthen our ability to advance new technologies and allow us to work more closely with our customers in Asia."

For Applied Materials, this is a significant addition of new capabilities in Singapore.

According to the IME and Applied Materials, the center will be the most advanced lab of its kind dedicated to wafer level packaging and will combine Applied Materials' leading-edge equipment and process technology with IME's leading research capability in 3D chip packaging.

The new facility positions Singapore as a global leader in semiconductor R&D and is expected to help accelerate the development and adoption of 3D packaging technology globally. Research activities are already underway with a team of over 50 personnel.

Center of Excellence in Advanced Packaging opening ceremony

A TSV-model cake being ceremonially cut at the launch of Center of Excellence in Advanced Packaging by (L-R): Randhir Thakur, EVP & GM, Applied Materials; Mr Leo Yip, chairman, EDB; Lim Hng Kiang, Minister for Trade & Industry; Michael Splinter, chairman & CEO, Applied Materials; Lim Chuan Poh, chairman, A*STAR; Kwong Dim-Lee, executive director, IME.

Traditionally, chips are connected to packages using wires attached to only their edges. This approach limits the possible number of connections from the chip and the long wire connections result in signal speed delays and power inefficiencies. With 3D chip packaging, multiple chips can be stacked on top of each other and connected with wiring that runs vertically through the stack called through-silicon vias (TSVs). When used to stack memory chips on logic chips, this technology is expected to reduce package size by 35 percent, decrease power consumption by 50 percent and increase data bandwidth by a factor of eight or more times.

Conceived to support research collaboration between Applied Materials and IME, the center will also allow both parties to pursue independent research initiatives including process engineering, integration and hardware development.

Lim Chuan Poh, chairman of A*STAR, said, "The combined efforts of Applied Materials and A*STAR's Institute of Microelectronics are a continuing testimony to A*STAR's spectrum of excellent and industry-relevant scientific capabilities. It reaffirms our strategy of leveraging a suite of capabilities to form meaningful and impactful public-private research alliances which catalyze the growth of private sector R&D activities in Singapore. This will create many high-value jobs locally and help to further anchor Singapore's semiconductor manufacturing base."

Dim-Lee Kwong, executive director of IME, added, "The Center of Excellence is a prime example of a strategic relationship fostered between two leading players in the global semiconductor value chain and will spur the development of innovative wafer-level packaging technologies to be implemented globally. This collaboration will enable the semiconductor industry to accelerate the adoption of 3D chip packaging."





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