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Taking advantage of MCU sleep modes to boost energy savings

Posted: 21 Mar 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Microcontrollers? energy consumption? sleep mode?

Microcontrollers (MCUs) are at the heart of almost every real-time application that requires prompt and predictable response to real-world events. Some of its applications are smart meters, wireless sensor nodes, or mobile health monitoring products. In many of these applications the MCU relies on sophisticated sleep mode techniques that suspend most or all of its operations to minimize energy consumption, allowing it to run for years or even decades on limited energy sources.

These real-time low-energy environments pose special challenges for the designer and programmer because the same sleep states that reduce an MCU's energy consumption often also reduce its ability to quickly respond to an event.

Low-power modes typically range from a light sleep or standby mode, through deep-sleep, to off (figure 1). Each has a progressively lower level of CPU, memory, and I/O functionality as more peripheral blocks are switched off. The specific functionality of each idle, sleep, and deep-sleep mode varies from processor to processor but the fundamentals are the same. Generally, the deeper the sleep, the less power is consumed by the MCU.

Figure 1: Typical microcontroller sleep modes.

Sleep is simple
The simplest mode for the designer to deal with is the sleep or standby mode. This enables a quick return to active mode, usually via an interrupt. But the cost for this level of responsiveness and simplicity is relatively high power consumption.

In sleep mode, the MCU's high-frequency clock oscillator remains running, but the clock tree that drives the CPU circuitry is disabled. This enables the CPU to resume executing instructions on the next clock cycle following the wake-up trigger. MCUs developed during the last decade employ extensive clock gating to cut off the clock signal to circuits that are not needed on any given cycle. This mode effectively provides clock gating across the entire CPU. However, the primary clock needs to continue to run to guarantee this level of response.

A number of advanced MCUs use on-chip phase-locked loops (PLLs), generally driven by a low-frequency quartz crystal, to generate the various clocks used by the processor core and other peripherals. For maximum energy saving these PLLs are best powered down when the blocks they drive are expected to be inactive. PLLs call for a constant current to maintain a lock. When starting up, it therefore takes time before the PLL is ready to provide a stable clock signal.

In standby mode, the high-frequency peripheral clock trees are commonly kept active, allowing autonomous functioning of high-speed peripherals such as direct memory access (DMA), high-speed serial ports, analog-to-digital and digital-to-analog converters, and AES encryption/decryption. RAM remains active and can be accessed by the DMA controller, allowing data retrieved by peripherals to be stored without CPU intervention. The MCU's pointer and configuration registers' states are preserved, also to minimize delay.

When a processor core is fully powered down, its software state must be saved to memory C either battery-backed SRAM or flash. Restoration can take thousands of clock cycles as this state data is fetched from the backup memory. A lighter sleep mode may keep the PLLs running and the core registers powered, albeit at a lower voltage, to allow them to 'drowse' with a lower power draw than during normal operation.

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