Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Electronics firms clamour for more collaboration

Posted: 15 Mar 2012 ?? ?Print Version ?Bookmark and Share

Keywords:3D transistor? EDA tools? silicon integration? 3D chip stacks?

In a Cadence Design Systems Inc. user event, executives of Cadence, Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) and ARM Ltd called for other companies to step up their collaborations to deal with the growing complexity of technologies of semiconductor design.

"Silicon integration and complexity will be a real challenge," said Lip-Bu Tan, chief executive of Cadence, noting 20nm chips with 8 billion transistors in the works.

Tan cited Apple, Oracle, Google and Facebook as examples of companies engaged in "applications-driven system design," spanning everything from silicon to software. "This will begin changing the landscape of semiconductor design," said Tan.

Lip-Bu Tan

Tan: Mobile, video and cloud are driving system design.

"We have lots of products coming out at the eight-billion transistor level, just two billion transistors is becoming pass," said Rick Cassidy, president of TSMC North America, "Working earlier together is an imperative to have the solution set in place," he added.

ARM, Cadence and TSMC provided an example of such collaboration with the announcement of a recent tape out of an ARM Cortex A15 core in a TSMC 20nm process using Cadence tools.

At 20nm double patterning with 193mm lithography becomes a requirement, Cassidy said. At 14 nm, certain critical layers will require triple patterning with 193mm litho, he said. Beyond that, "there's a race between extreme ultraviolet and direct write litho techniques" for the future of lithography, he added.

3D transistors and chip stacks are logical candidates for the next big collaboration between the three companies, suggested Tom Lantzsch, executive vice president of ARM, in his keynote.

"3D transistors have all new challenges in design and it's critical for us" to master them, Lantzsch said. With the 20nm A15 tape out, "we have never been involved earlier, and we need to do more of this," he added.

Rick Cassidy

Cassidy: The 14 nm processes will require some triple-patterning.

As for 3D chip stacks, they "really change the way you should be thinking about how you architect new products," said TSMC's Cassidy in his keynote. "There's a great deal system designers can do to solve problems in different ways then they have ever done before," he said, noting TSMC now has 3D IC solutions as part of its 12.0 reference flow.

Cassidy also referred to a MugFET as part of his talk, but didn't clarify whether it was a 3D transistor. For its part, Cadence has announced silicon blocks for Wide I/O memory, a key component for 3D stacks expected in mobile applications processors. It has not yet released an EDA tool for 3D stacking, a spokesman said.

All sides agreed the long term outlook for the semiconductor business is strong.

"Clearly Q1 is a little but soft, but all execs I talk to say Q2 is looking stronger," said Tan, noting one industry index is up over 50 percent for the first time since late 2010.

"Semiconductors are at the heart of all devices. I convinced my two sons to focus on semiconductors and become EEsI am so proud of themit's a golden opportunity going forward," Tan said.

- Rick Merritt
??EE Times

Article Comments - Electronics firms clamour for more c...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top