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Grasp the density requirements at 28 nm

Posted: 29 Mar 2012 ?? ?Print Version ?Bookmark and Share

Keywords:28 nm? cell design level? Chemical Mechanical Polishing?

Discussions with customers around the world have exposed a surprising new messagethat, at 28 nm, they have to care about density at the cell design level "like never before." It's surprising because density has historically been a manufacturing issue that was handled post tapeout or during chip assembly. However, where and how density is handled in the design process has evolved significantly along with the process technologies (figure 1). In this article, I'll take a look at how density has evolved from a back-end manufacturing issue that was of little interest to designers to a design concern that affects the layout of standard cell libraries.

Figure 1: Responsibility for density checking and management has moved progressively up the production line as nodes decrease and designs become more compact.

In this discussion, density refers to drawn area of polygons in a given area on a given layer in a layout. The size of the area in which the density is calculated, called the "window," depends on the process effect that is driving the check. For instance, some process effects are very local (microns or less), while others have much larger interaction distances (up to 100s of microns). In fact, a basic processChemical Mechanical Polishing (CMP), for instancewill have different interaction distances on different layers, resulting in different window sizes for each of the layers.

Figure 2: The growth in density rules and design rules over technology node advancements.

In technologies before 130 nm, density was treated as a manufacturing issue, and the responsibility of the foundry. At that time, the window size for density checks was between 100?m and 300?m, depending on the foundry and layer. That window size was 300-600 times the size of the minimum pitch, meaning that, in these designs, the density was being averaged over a lot of layout. The cell designer could easily follow the simple width and spacing design rules without worrying about density, unless the design was one of a small set of special structures, like capacitors. When the chip was finished, it went to the foundry, and the foundry added extra metal shapes in the empty spaces between the drawn polygons to even out the density variations. This was called "dummy" fill because the extra shapes weren't part of the circuit. In the beginning, the foundries did this without even telling their customers about it, since the process was assumed to have no impact on the electrical characteristics of the circuit.

However, with each new technology, the foundry has to solve a host of new process challenges. In solving those challenges, they often have to make decisions and compromises that add new constraints to the design rules. As you can see in figure 2, not only does the number of design rules steadily increase with each new technology, but the same effect also occurs with the density requirements. For instance, there might need to be separate rules for density inside and outside of the memories, or a new technology or layer might be more sensitive to variation in the density, and thus need a new rule for allowable density gradient. Each new technology has made the requirements for density more stringent, while at the same time adding more restrictions on how the layout can be manipulated to meet those requirements. The phrase "between a rock and a hard place" comes to mind, since the layout is being constrained both at the very local level (design rules) and at the macro level (density over an area).

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