Micron advances with 3D chips

Micron Technology Inc. has revealed that it is adding new supporters and specifications with regard to its planned release of the Hybrid Memory Cube in 1H13, an ultra-dense memory device. The move by the company is in response to the increasing interest surrounding 3D chip ICs.

The memory maker hopes to name two new supporters in the next few weeks to its current slate of six companies including Altera, OpenSilicon, Samsung, Xilinx and IBM that have made a prototype cube in a 32nm process. In September last year, Intel showed a research project on a physical-layer device that worked with Micron's cube.

The Hybrid Memory Cube is a stack of four to eight DRAM die linked in a 3D IC chip stack using through silicon via (TSV). They are joined to a logic die that can handle both the RAS/CAS memory-array access jobs of a DRAM chip and the system memory controller functions typically done by a separate chip.

Designers envision placing the Micron stack on a chip substrate next to a server or network processor to provide new levels of fast memory access for high performance systems. Micron says it will deliver early next year 2GB and 4GB versions of the stack providing aggregate bi-directional bandwidth of up to 160GB/s.

Members of Micron's consortium are still debating exactly what jobs the logic layer in the stack should support, particularly as the latest server processors already embed memory controllers. Micron prefers to provide the full complement of DRAM and system control in the cube.

Consortium makes hybrid memory standard Micron and Samsung have announced an open consortium that centers on hybrid memory cube. This technology merges DRAM and logic processes into one package to deliver potential power efficiency, bandwidth, density and scalability advantages against traditional DRAM, noted the two companies.

The debate is one of the central issues in creating an interface for the cube. Micron and partners hope to deliver a draft of that interface in June, initially open only to members of its consortium of partners. Another issue is whether or how to support atomic transactions, a method for aggregating tasks particularly helpful for multicore processors.

The cube spec in development is described as a high-speed serial interface using a packet protocol. Micron hopes the group can finish the spec by the end of the year, making it generally available on a royalty-free basis.

Micron is not alone in the pursuit of a 3D memory stack. The Jedec group is working on a follow on to the 12.8Gb/s Wide I/O interface that targets mobile applications processors. The so-called HB-DRAM or HBM effort is said to target a 120-128GB/s interface and is led by the Jedec JC-42 committee including representatives from Hynix and other companies.

- Rick Merritt
??EE Times