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Design IP supports LPDDR3 memory standard

Posted: 09 Apr 2012 ?? ?Print Version ?Bookmark and Share

Keywords:design IP? memory standard? LPDDR3?

Cadence Design Systems Inc. has expanded its design IP portfolio with the release of the memory IP solution supporting the LPDDR3 mobile memory standard. According to the company, the design IP offers high bandwidth and low power consumption required by smartphones and tablets.

The LPDDR3 memory IP solution includes integrated controller and PHY support, virtual prototyping, verification IP and Allegro design-in kits to accelerate implementation and reduce design risk.

The LPDDR3 standard will offer an extension to the bandwidth of LPDDR2, reaching 6.4GB/s per die (1600MT/s per pin) and allowing 12.8GB/s for a dual channel configuration. It will support both PoP and discrete packaging types, allowing versatile usage. LPDDR3 will preserve the power-efficient features of LPDDR2, allowing for fast clock stop/start, low-power self-refresh and smart array management.

The company said the configurable design IP allows the LPDDR3 standard to be combined with others in a single controller and PHY to enable SoCs that support multiple memory standards, making one design usable by multiple markets.

As part of the LPDDR3 launch, Cadence has upgraded the bandwidth management enginePlacement Queue 2.2to optimize the way memory is accessed to improve overall system performance and power consumption.

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