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Resistive RAM based on silicon dioxide

Posted: 11 Apr 2012 ?? ?Print Version ?Bookmark and Share

Keywords:resistive RAM? silicon dioxide? metal-oxide film?

A team of researchers at the University of Pennsylvania has developed a novel resistive-switching memory device based on silicon dioxide. The device was marked by the inclusion of atomically dispersed platinum on a random basis, the variation of the distances between the platinum atoms and their relationship to a quantum mechanical property known as the electron localization length.

Silicon dioxide is generally considered an insulator but in films of nanometer-scale thickness and random dispersion of platinum atoms, it can be made to display a memory effect. The development of a resistive-switching non-volatile memory based on the CMOS-compatible material offers the prospect of an ReRAM memory with useful properties but a simpler material structure to some alternative proposals based on metal-oxide films, noted the researchers.

The behavior is ascribed to the tunneling of electrons between atomically dispersed platinum in amorphous silicon dioxide thin films between platinum and molybdenum electrodes. It is said that the trapped electrons and the local Coulomb barriers that can also be created can "choke off" the electron passage in the nearby nanometallic paths, making non-volatile memory possible. Nanoparticles of platinum, which may not even be metallic according to their optical responses, are sometimes present at higher platinum concentrations but are not required for the operation of the device.

The electron transport system through the material is generally applicable to random metal-insulator mixes and has been demonstrated in silicon oxide and silicon nitride glasses with platinum inclusions as well as in perovskite transition metal oxides.

I-Wei Chen, member of the research team, told EE Times that the materials are quite easy to make by the use of co-sputtering on to a substrate, although the exact composition together with final film thicknesses are significant in tuning the memory effect and voltage scheme. The research group has made individual devices with sizes down to 20 x 20? with film thicknesses of between 5nm and 30nm to 40nm. "I see no evidence why it should not scale," Chen stated.

Bipolar resistance switching
In previous papers, Chen's team has reported on a device that showed uniform bipolar resistance switching behavior with an operation below 100ns and a resistance on/off ratio of more than 100 and greater than 10 years retention time.

In terms of cycling endurance, the team has not yet done strict testing although they have put devices through thousands of programming and erase cycles, Chen said. He added that achieving the cycling endurance of nanometric NAND flash memory at 10^4 or 10^5 cycles represented a relatively easy goal. "I don't see a problem exceeding flash memory. Whether it could be used as a DRAM at 10^10 or 10^11 cycles I don't know."

The use of different electrodes is significant as there is a work function dependency in the switching. However, the use of molybdenum and platinum in particular is not required, noted Chen. "We chose platinum as the top electrode because it is very durable; useful for test devices."

In the present arrangement, the change from high resistance state (HRS) to low resistance state (LRS), which Chen calls onswitching, occurs at about -1V while the switching from LRS to HRS can be tuned to take place at voltages down to 1V but in the range of 1-10V. Reading the state of the memory requires a lower voltage of about 0.5V but could be taken down to 0.2V, Chen added.

These memories are not thought to be filamentary and unlike other ReRAMs, the insulator-metal transition in nanometal ReRAMs can be triggered by UV irradiation without an electric field.

Chen's group has not yet made any devices with nm-scale lateral minimum geometries nor has it produced any arrays of the memory devices. One of the reasons for this is that as the memory device is bipolar it will require a circuit isolation device to prevent cross-talk in an array.

The development of smaller geometry devices and arrays represents an obvious next step for the research. "We would like some companies to get interested and see if it can be done in a wafer fab setting," Chen expressed.

- Peter Clarke
??EE Times

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