Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Xilinx, Intel aid EDA startup

Posted: 12 Apr 2012 ?? ?Print Version ?Bookmark and Share

Keywords:EDA? venture capital? chip design? logic synthesis?

Xilinx Inc. and Intel Capital, the venture capital arm of Intel Corp., have provided an unspecified amount of funding to Oasys Design Systems Inc., Oasys revealed. The EDA startup that offers physical synthesis tools for designing and implementing ICs with more than 20 million gates, said it would use the Series B funding to expand its research and development team and further expand its worldwide support structure.

"Oasys' technology has the potential to positively impact the design flow for VLSI chip implementation," noted Shishpal Rawat, director of business enabling programs for Intel's design technology solutions group. "This is a new way of thinking for next-generation chip design implementation."

Oasys claims its RealTime Designer is the first design tool for physical register transfer level (RTL) synthesis of 100-million gate designs and produces better results in a fraction of the time needed by traditional logic synthesis products. RealTime Designer features a unique RTL placement approach that eliminates unending design closure iterations between synthesis and layout, according to the company.

Oasys has announced several customers among U.S. semiconductor companies, including Texas Instruments Inc., Qualcomm Inc. and Xilinx.

- Dylan McGrath
??EE Times





Article Comments - Xilinx, Intel aid EDA startup
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top