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Addressing integration concerns with SiP technologies

Posted: 17 Apr 2012 ?? ?Print Version ?Bookmark and Share

Keywords:system-in-package? through-silicon via? design-for-test?

The growing opportunities and requirements for system-in-package (SiP) technologies have become a driving force in the electronics and semiconductor industry. A number of companies are focused on maximizing the benefits and meeting the challenges that SiP brings.

Some SiP technologies, such as wirebonded multichip modules and advanced MCMs, have been around for decades; others, such as package-on-package stacking, are more recent. Such newer technologies as 2.5-D interposers and 3-D through-silicon via (TSV) can bring new challenges along with new capabilities.

Depending on the design and application space, SiPs can:
- Improve performance with tighter integration and co-design;
- Increase power efficiency, with shorter data transmission channels;
- Enable heterogeneous integration via different technologies;
- Lower total cost by reducing the system size and bill of materials (BOM);
- Reduce complex system-on-chip (SoC) development for shorter time-to-market; and
- Miniaturize devices by stacking components, vs. side-by-side layout.

However, SiP products also have unique challenges.

As data density, bandwidth and frequency increase, electrical parasitics must be reduced. This generally requires shorter data paths and more of them, which means finer pitches. These form factors, pitches and mechanical structures drive the interconnection technologies required by the SiP solution.

Such adjustments to design and fabrication must take into account equipment capability and cost, bonding accuracy and yield, as well as advanced materials.

Reaching the required quality, cost and yield calls for a new approach to process, equipment and materials. One challenge of SiP implementation is that the devices to be integrated often arrive in different formats, such as wafers, individual units or intermediate carriers.

To reach higher performance levels and density, devices often need to be designed, simulated and fabricated in parallel with the SiP solutions. For high-frequency data paths, that means leveraging shorter chip-to-chip distances with low-latency interconnections to improve power efficiency and reduce die area.

I/O definition (planning, placement and optimization) and 3-D floor planning become more critical in the early phases of the design flow. Increasingly, co-design is required across divergent tool platforms, teams or design functions, and even across different companies. This adds time and uncertainty to the design process.

It is important to test the intermediate and final process steps to get the best yield, quality and cost. Intermediate testing can be difficult because the process steps have various formats, and pieces have to be tested apart from the whole. Final testing can be difficult because a more-complex final device requires more-complex and more-costly equipment and algorithms to evaluate proper functionality.

One solution is proactive design-for-test (DFT) on each part of the product.

The need for standardization of advanced SiP technologies will grow as design, packaging, device processing and test become more fragmented and cross boundaries among companies and working environments. Standardization across the process toward final product is often uncharted territory.

All these challenges affect costs for engineering, equipment, manufacturing, procurement and liability for quality and yield. The semiconductor market encourages companies to focus on what they want and outsource the rest. In an SiP environment with more devices and complex intermediate processes, many production models must be redefined. That affects the financial decisions involved in product development, especially for companies with less ability or penchant for investment in unproven solutions.

Five levels of complexity
There are five levels of complexity in SiP solutions, depending on the implementation considered and the benefits to be achieved.

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